Vendor: Altera Category: Single-Protocol PHY

Multi-Rate Ethernet PHY FPGA IP

The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device re…

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Overview

The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device reconfiguration. This IP allows the creation of a 1G to 10G configuration that allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G.The 2.5G and 5G Ethernet configurations were introduced to support higher bandwidth on widely deployed CAT5e and CAT6 cabling in enterprise and metro area networks.

Key features

  • Implements the Ethernet protocol as defined in clause 36 of the IEEE 802.3 2005 standard.
  • Consists of a physical coding sublayer (PCS) function and an embedded physical medium attachment (PMA).
  • Dynamically switchable PHY operating speed.
  • 1G/2.5G, 2.5G, 10M/100M/1G/2.5G, 1G/2.5G/10G (MGBASE-T), 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M, 100M, 1G, 2.5G, 10G (MGBASE-T) operating modes.
  • Users needing Copper-PHY capability for USXGMII, MGBASE-T modes will need to use an external PHY chip.

Block Diagram

Multi-Rate Ethernet PHY FPGA IP block diagram

Specifications

Identity

Part Number
Multi-Rate Ethernet PHY FPGA IP
Vendor
Altera
Type
Silicon IP

Files

Product Sheet Download

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Provider

Altera
HQ: USA
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Frequently asked questions about Single-Protocol PHY IP

What is Multi-Rate Ethernet PHY FPGA IP?

Multi-Rate Ethernet PHY FPGA IP is a Single-Protocol PHY IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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