Can MIPI and MDDI Co-Exist?
Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?
Vendor:
Mixel, Inc.
Category:
Single-Protocol PHY
LVDS Serializer IP
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
Overview
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
Key features
- 25-165 MHz clock support
- Up to 1.25 Gbps bandwidth
- Up to 5 Gbps data throughput
- Low power CMOS design
- Low swing LVDS for low EMI
- PLL requires no external components
- Core Voltage & 3.3V dual power supply
- Optional transmit pre-emphasis
- Programmable parallel data width
- Rising/falling edge data strobe
- Compatible with TIA/EIA-644 LVDS Standard
Block Diagram
MXL-SR-LVDS block diagram
Specifications
Identity
Part Number
MXL-SR-LVDS
Vendor
Mixel, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Single-Protocol PHY IP
What is LVDS Serializer IP?
LVDS Serializer IP is a Single-Protocol PHY IP core from Mixel, Inc. listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.