A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection
By Jonas Elmiger, Fabian Stuber, Oscar Castañeda, Gian Marti, Christoph Studer
Department of Information Technology and Electrical Engineering, ETH Zurich, Switzerland
We present the first single-input multiple-output (SIMO) receiver ASIC that jointly performs jammer mitigation, channel estimation, and data detection. The ASIC implements a recent algorithm called siMultaneous mitigAtion, Estimation, and Detection (MAED). MAED mitigates smart jammers via spatial filtering using a nonlinear optimization problem that unifies jammer estimation and nulling, channel estimation, and data detection to achieve state-of-the-art error-rate performance under jamming. The design supports eight receive antennas and enables mitigation of smart jammers as well as of barrage jammers. The ASIC is fabricated in 22 nm FD-SOI, has a core area of 0.32 mm2, and achieves a throughput of 100 Mb/s at 223 mW, thus delivering 3× higher per-user throughput and 4.5× higher area efficiency than the state-of-the-art jammer-resilient detector.
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