Fragmentation to Standardization: Evaluating RISC-V’s Path Across Data Centers, Automotive, and Security
By Saumitra Jagdale, Open Cloudware
embedded.com, November 21, 2025
Despite being preferred by newly established companies that had the same needs for ISAs as their competition, they lacked the time and resources to deal with costly, complex proprietary ISAs.
While RISC-V was rightly preferred because of its open standard community and accessibility, it was not yet ready to replace competing architectures. Its fragmentation and immaturity often made prospective users lean back toward the secure capabilities of ARM and x86. There were also real technical challenges that, if not addressed, risked slowing RISC-V’s adoption compared to its predecessors.
How RISC-V Emerged Amid ARM and x86
Because it was so new, RISC-V had not yet matched the maturity of its counterparts, ARM and x86. With their vast ecosystems, these proprietary ISAs provided strong support for ecosystem development and performance optimization.
To read the full article, click here
Related Semiconductor IP
- 64-Bit 8-stage superscalar RISC-V processor
- Multi-core capable RISC-V processor with vector extensions
- 32 Bit - Embedded RISC-V Processor Core
- ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications
- ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
Related Articles
- An Open-Source Approach to Developing a RISC-V Chip with XiangShan and Mulan PSL v2
- RISC-V in 2025: Progress, Challenges,and What’s Next for Automotive & OpenHardware
- Evaluating Lossless Data Compression Algorithms and Cores
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace