Overview
The Lattice 2.5 Gbps Ethernet PCS IP core implements the state machine functions for the physical coding sublayer (PCS) described in the IEEE 802.3z (1000BaseX) specification. Note that the IEEE specification describes a PCS that operates at 1Gbps. Therefore, this 2.5G PCS IP core is non-standard with respect to the IEEE specification.
The two major non-compliances are data rate (2.5 Gbps instead of 1 Gbps) and GMII data bus width (16 bits instead of 8 bits).
This PCS IP core was specifically developed to operate with the Lattice 2.5 Gbps MAC IP core. The Lattice 2.5G PCS and MAC IP cores are 100% compatible and can be used to create a full PHY/MAC Ethernet data path that operates at 2.5 Gbps.
This document describes the 2.5 Gbps Ethernet PCS IP core’s operation, and provides instructions for generating the core through the Lattice IPexpress™ tool, and for instantiating, synthesizing, and simulating the core.
The 2.5 Gbps Ethernet PCS IP core converts GMII frames into 8-bit code groups in both transmit and receive directions and performs auto-negotiation with a link partner as described in IEEE 802.3z specification.
Learn more about Single-Protocol PHY IP core
Lattice Prompt pairs with AI agentic tools developers already use, combining them with Lattice design tools, knowledge base, and documentation to turn natural language inputs into validated responses, dramatically accelerating FPGA development while optimizing design performance and capability.
First announced on May 4, 2026, the acquisition creates the industry's most complete secure management and control platform.
The acquisition brings together Lattice’s industry-leading low power FPGAs with AMI’s industry‑leading platform firmware and infrastructure manageability solutions for cloud and AI to create a complete portfolio of secure management and control solutions.
The collaboration demonstrates a real-time AI sensor fusion architecture that integrates TI mmWave radar and camera sensors using NVIDIA Holoscan Sensor Bridge running on Lattice’s low power FPGA. The FPGA acts as a companion chip delivering synchronized sensor data directly into GPU-accessible memory to enable low-latency and robust perception for robotics and industrial edge AI applications.
Sets new standard for secure control FPGAs with full CNSA 2.0-compliant post-quantum cryptography, crypto-agility, and hardware Root of Trust for next-generation infrastructure
Lattice Semiconductor today announced that the company expanded its small FPGA portfolio with new, high I/O density options in the Lattice Certus™-NX FPGA and Lattice MachXO5™-NX FPGA device families.
