Processor Architecture for High Performance Video Decode
Processor Architecture for High Performance Video Decode
Vendor:
Lattice Semiconductor Corp.
Category:
Filters Transforms
Crest Factor Reduction IP
Crest factor reduction (CFR) selectively reduces the peak-to-average ratio (PAR) of wideband digital signals, such as those used …
Overview
Crest factor reduction (CFR) selectively reduces the peak-to-average ratio (PAR) of wideband digital signals, such as those used in third-generation (3G) code division multiple access (CDMA) or long term evolution (LTE) wireless applications.
The Lattice peak cancellation crest factor reduction (PC-CFR) IP core is part of the digital front end (DFE) suite of IP cores optimized for HetNet applications. The core is highly programmable and can be customized to achieve the desired resource vs performance trade off. The core is optimized for use with ECP3 FPGA family and achieves up to 4dB of PAR reduction for LTE signals.
The Lattice peak cancellation crest factor reduction (PC-CFR) IP core is part of the digital front end (DFE) suite of IP cores optimized for HetNet applications. The core is highly programmable and can be customized to achieve the desired resource vs performance trade off. The core is optimized for use with ECP3 FPGA family and achieves up to 4dB of PAR reduction for LTE signals.
Key features
- The Lattice PC-CFR IP supports between 1 to 4 antennas
- The core can be configured for clock-to-sample ratios of 1, 2 or 4
- Provides 1, 2 or 3 sequential detection and cancellation stages to remove peaks
- Cancellation pulses may be real or complex
- Pulse coefficients can be pre-configured at generation time through coefficient file or configured during operation through the Wishbone interface
- Each filter stage can be independently configured with detection target peak threshold and cancellation pulse coefficients
- Number of clip engines for each filter stage can be independently configured
- The maximum cancellation pulse length is configurable.
- The IP provides parallel or TDM (Time-Division Multiplexing) quadrature (I & Q) format for input/output mode
- Configurable data width
- Configurable coefficient width
- Option for input/output gain
Block Diagram
CFR block diagram
Specifications
Identity
Part Number
CFR
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about Filters Transforms IP core
No size fits all for signal processing on FPGA (RF Engines)
No size fits all for signal processing on FPGA (RF Engines)
Employing general-purpose processors for radio DSP
Employing general-purpose processors for radio DSP
Do's and Don'ts of Architecting the Right FPGA Solution for DSP Design
Finally a Practical ''Do and Don't'' primer on architecting FPGA solutions for DSP design. With more do's than don’ts, the article is a down-to-basics look at how to avoid the pitfalls and realize device benefits
10 FPGA Design Techniques You Should Know
Regardless of whether you are using VHDL, System Verilog, or a different design capture language, there are a number of universal design techniques with which FPGA engineers should be familiar, from the very simple to the most advanced.
How to implement double-precision floating-point on FPGAs
The real results of a double-precision matrix multiply core that can easily be extended to a full DGEMM benchmark are demonstrated.
Frequently asked questions about Filters and Transforms IP cores
What is Crest Factor Reduction IP?
Crest Factor Reduction IP is a Filters Transforms IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.
How should engineers evaluate this Filters Transforms?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Filters Transforms IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.