Vendor: Lattice Semiconductor Corp. Category: DDR

DDR3 SDRAM Controller

The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory contr…

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Overview

The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR3 memory devices/modules compliant with JESD79-3, DDR3 SDRAM Standard, and provides a generic command interface to user applications. The DDR3 SDRAM is the next-generation DDR SDRAM memory technology which features faster speed, mitigated SSO, and reduced routing due to “fly-by” routing signals to SDRAM instead of low skew tree distribution. This core reduces the effort required to integrate the DDR3 memory controller with the remainder of the application and minimizes the need to directly deal with the DDR3 memory interface.

DDR3 SDRAM Controller IP Core Pinout Generation Utility

The DDR3 Pinout Generation Utility is a GUI tool capable of generating the pinout and preference files that contain information for a design that uses the DDR3 SDRAM Controller IP core. More information about this utility, including downloads and documentation is available here.

Key features

  • Support for all LatticeECP3 “EA” devices
  • Interfaces to Industry Standard DDR3 SDRAM components and modules compliant with JESD79-3, DDR3 SDRAM Standard
  • Interfaces to DDR3 SDRAM at speeds up to 400 MHz / 800 Mbps in -8 speed grade devices
  • Supports memory data path widths of -8, -16, -24, -32, -40, -48, -56, -64 and -72 bits
  • Supports x4, x8, and x16 device configurations
  • Support for unbuffered DDR3 DIMM and DDR3 RDIMM module
  • Supports up to one DIMM and two ranks per DIMM
  • Programmable burst lengths of 8 (fixed), chopped 4 or 8 (on-the-fly), or chopped 4 (fixed)
  • Programmable CAS latency
  • Programmable CAS Write Latency
  • Read burst type of nibble sequential or interleave
  • Supports automatic DDR3 SDRAM initialization and refresh
  • Automatic Write Leveling for each DQS for DIMM applications. Option to switch of write leveling for On-board memory applications.
  • Supports Power Down Mode
  • Supports Dynamic On-Die Termination (ODT) controls
  • Termination Data Strobe (TDQS) for x8 widths only
  • LatticeECP3 I/O primitives manage read skews (Read Leveling equivalent)
  • Automatic Programmable Interval Refresh or User Initiated Refresh
  • Option for controlling memory reset outside the controller

Block Diagram

DDR3 block diagram

Specifications

Identity

Part Number
DDR3
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP
Controller / PHY
Controller

Standards & Interfaces

Memory
DDR3

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Lattice Semiconductor Corp.

Learn more about DDR IP core

DDR3 memory interface controller IP speeds data processing applications

In order to fully capitalize on the benefits of DDR3 memories, it is important to have an efficient and easy to use DDR3 memory interface controller. A video processing application provides a good example of the key requirements of a DDR3 memory system and the features needed from a DDR3 Interface in similar stream-oriented data processing systems.

Microcontroller Design in FPGAs

The union of Microcontroller Unit (MCU) intellectual property (IP) cores with FPGAs provides a far more flexible hardware platform than traditional MCU ASSPs.

Frequently asked questions about DDR Interface IP

What is DDR3 SDRAM Controller?

DDR3 SDRAM Controller is a DDR IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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