Vendor: Lattice Semiconductor Corp. Category: DDR

DDR SDRAM Controller - Non-Pipelined

This version of the Lattice DDR SDRAM Controller does not have pipelining, and is significantly smaller than the pipelined versio…

Controller View all specifications

Overview

This version of the Lattice DDR SDRAM Controller does not have pipelining, and is significantly smaller than the pipelined version. DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz. DDR SDRAM is similar in function to the regular SDRAM but doubles the bandwidth of the memory by transferring data twice per cycle on both edges of the clock signal, implementing burst mode data transfer.

The DDR SDRAM Controller is a parameterized core giving users the flexibility for modifying data widths, burst transfer rates and CAS latency settings in a design. In addition, the DDR core supports intelligent bank management, which is done by maintaining a database of "all banks activated" and the "rows activated" in each bank. With this information, the DDR SDRAM Controller decides if an active or pre-charge command is needed. This effectively reduces the latency of read/write commands issued to the DDR SDRAM.

Key features

  • Performance of Greater than 133MHz (266 DDR)
  • Interfaces to JEDEC Standard DDR SDRAMs
  • Supports DDR SDRAM Data Widths of 16, 32 and 64 bits
  • Supports up to 8 External Memory Banks
  • Programmable Burst Lengths of 2, 4, or 8
  • Programmable CAS Latency of 1.5, 2.0, 2.5 or 3.0
  • Byte-level Writing Supported
  • Supports Power-down and Self Refresh Modes
  • Automatic Initialization
  • Automatic Refresh During Normal and Power-down Modes
  • Timing and Settings Parameters Implemented as Programmable Registers
  • Complete Synchronous Implementation

Block Diagram

DDRCT-NP block diagram

Specifications

Identity

Part Number
DDRCT-NP
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about DDR IP core

Lattice Collaborates with TI to Accelerate Edge AI for Robotics and Industrial Applications

The collaboration demonstrates a real-time AI sensor fusion architecture that integrates TI mmWave radar and camera sensors using NVIDIA Holoscan Sensor Bridge running on Lattice’s low power FPGA. The FPGA acts as a companion chip delivering synchronized sensor data directly into GPU-accessible memory to enable low-latency and robust perception for robotics and industrial edge AI applications.

Frequently asked questions about DDR Interface IP

What is DDR SDRAM Controller - Non-Pipelined?

DDR SDRAM Controller - Non-Pipelined is a DDR IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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