FPGA-based Ethernet switches for real-time applications
Lattice Semiconductor and Flexibilis have released a Gigabit Ethernet Switch IP core that is scalable, non-blocking, and extensible
Vendor:
Lattice Semiconductor Corp.
Category:
Ethernet
2.5Gbps Ethernet MAC IP Core
The 2.5GMAC IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
Overview
The 2.5GMAC IP core supports the ability to transmit and receive data between a host processor and an Ethernet network. The main function of the Ethernet MAC is to ensure that the Media Access rules specified in the 802.3 IEEE standard are met while transmitting a frame of data over Ethernet. On the receiving side, the Ethernet MAC extracts the different components of a frame and transfers them to higher applications through the FIFO interface.
The 2.5GMAC IP core transmits and receives data between a client application and an Ethernet network. The main function of the Ethernet MAC is to ensure that the Media Access rules specified in the 802.3 IEEE standard are met while transmitting and receiving Ethernet frames.
On the receiving side, the Ethernet MAC extracts the different components of a frame and transfers them to high-er applications through the client FIFO interface. The data received from the GMII interface is first buffered until sufficient data is available to be processed by the Receive MAC (Rx MAC).
The Preamble and the Start-of-Frame Delimiter (SFD) information are then extracted from the incoming frame to determine the start of a valid frame. The Receive MAC checks the address of the received packet and validates whether the frame can be received before transferring it into the FIFO. Only valid frames are transferred into the FIFO (runts and fragments are discarded). The Rx MAC also provides a statistics vector on a per packet basis that can be used by the application. The 2.5GMAC IP core always calculates CRC to check whether the frame was received error-free.
On the transmit side, the Tx MAC is responsible for controlling access to the physical medium. The Tx MAC reads data from an external client Tx FIFO, formats this data into an Ethernet packet and passes it to the GMII module.
The Tx MAC reads data from the Tx Client FIFO when the client indicates a packet is available, and the Tx MAC is in its appropriate state. The Tx MAC pre-fixes the Preamble and the Start-of-Frame Delimiter information to the data and appends the Frame Check Sequence at the end of the data.
The 2.5GMAC IP core transmits and receives data between a client application and an Ethernet network. The main function of the Ethernet MAC is to ensure that the Media Access rules specified in the 802.3 IEEE standard are met while transmitting and receiving Ethernet frames.
On the receiving side, the Ethernet MAC extracts the different components of a frame and transfers them to high-er applications through the client FIFO interface. The data received from the GMII interface is first buffered until sufficient data is available to be processed by the Receive MAC (Rx MAC).
The Preamble and the Start-of-Frame Delimiter (SFD) information are then extracted from the incoming frame to determine the start of a valid frame. The Receive MAC checks the address of the received packet and validates whether the frame can be received before transferring it into the FIFO. Only valid frames are transferred into the FIFO (runts and fragments are discarded). The Rx MAC also provides a statistics vector on a per packet basis that can be used by the application. The 2.5GMAC IP core always calculates CRC to check whether the frame was received error-free.
On the transmit side, the Tx MAC is responsible for controlling access to the physical medium. The Tx MAC reads data from an external client Tx FIFO, formats this data into an Ethernet packet and passes it to the GMII module.
The Tx MAC reads data from the Tx Client FIFO when the client indicates a packet is available, and the Tx MAC is in its appropriate state. The Tx MAC pre-fixes the Preamble and the Start-of-Frame Delimiter information to the data and appends the Frame Check Sequence at the end of the data.
Key features
- Compliant to IEEE 802.3-2005 standard
- Generic 8-bit host interface
- 16-bit wide internal data path
- Generic transmit and receive FIFO interface
- Full-duplex operation
- Transmit and receive statistics vector
- Programmable Inter-Packet Gap (IPG)
- Multicast address filtering
- Supports:
- Full-duplex control using PAUSE frames
- VLAN tagged frames
- Automatic padding of short frames
- Multicast and Broadcast frames
- Optional FCS transmission and reception
- Jumbo frames of any length
Block Diagram
PT5-MAC block diagram
Specifications
Identity
Part Number
PT5-MAC
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Ethernet IP cores
What is 2.5Gbps Ethernet MAC IP Core?
2.5Gbps Ethernet MAC IP Core is a Ethernet IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.
How should engineers evaluate this Ethernet?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.