The UALink Controller delivers ultra-low latency and high-bandwidth interconnects that enable seamless scale-up connectivity between AI accelerators
- UALink
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The UALink Controller delivers ultra-low latency and high-bandwidth interconnects that enable seamless scale-up connectivity between AI accelerators
Verification IP for AMBA AXI4-Stream
Synopsys Verification IP (VIP) for Arm® AMBA® AXI4-Stream™ provides a comprehensive set of protocol, methodology, verification, a…
Synopsys Verification IP (VIP) for Arm® AMBA® APB™ provides a comprehensive set of protocol, methodology, verification, and produ…
Synopsys Verification IP (VIP) for Arm® AMBA® AHB™ provides a comprehensive set of protocol, methodology, verification, and produ…
VIP for Compute Express Link (CXL)
Synopsys Verification IP (VIP) for CXL provides verification of design implementations based on CXL specifications which can be u…
MIPI D-PHY and FPD-Link(LVDS) Combinational Transmitter for TSMC 22nm ULP
The MIPI D-PHY and FPD-Link (LVDS) combinational Transmitter is useful 4 Data Channel driverhard macro for DSI® of TSMC 22nm ULP process.
Line-Rate UDP/IPv6 Offload for Modern FPGA Designs UOE6 is Atomic Rules’ next-generation UDP Offload Engine, purpose-built for IP…
Microsecond Channel (MSC/MSC-Plus) Controller
The MSC-CTRL IP core implements a high-speed serial interface controller designed to connect a microcontroller or SoC to external…
Silicon agnostic and fully compliant implementation of UALink_200 specification The Chip Interfaces UA Link TL IP Core is a high-…
Silicon agnostic and fully compliant implementation of UALink_200 specification The UA Link DL IP Core is a high-performance, sil…
The Ultra Accelerator Link (UALink) Verification IP (VIP) provides a bus functional model (BFM) with integrated automatic protoco…
Simulation VIP for AMBA CHI-C2C
Best-in-class Arm® AMBA® CHI-C2C Verification IP (VIP) for your IP, SoC, and System-level Design Testing Cadence provides a matur…
Brite provides full solution for the MIPI CSI interface, which receives the data from sensors in PHY layer, and then converts the…
Parallel to AHB bridge, following AMBA4 specifications
dos_parallel_AHB_bridge is a Parallel to AHB bridge, following AMBA4 specifications
I2S to AHB bridge, following AMBA4 specifications
dos_I2S_AHB_bridge is an I2S to AHB bridge, following AMBA4 specifications
TSMC N5A SD/eMMC PHY AG2 Platform
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC N3P SD/eMMC PHY North/South Poly Orientation MS add-on
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC N3P SD/eMMC PHY North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC N3E SD/eMMC PHY North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
TSMC N3A SD/eMMC PHY AG2 North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.