SONET/SDH OC-12 Transceiver/CDR
The SMS2012 SONET/SDH is a fully integrated Clock Data Recovery (CDR) SONET OC-3 interface core designed for multiple integration…
- Optical Transport
- Silicon Proven
- Now
- ANSI Bellcore ITU
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
SONET/SDH OC-12 Transceiver/CDR
The SMS2012 SONET/SDH is a fully integrated Clock Data Recovery (CDR) SONET OC-3 interface core designed for multiple integration…
Universal Asynchronous Receiver/Transmitter Module
The UARTmodule is part of Inicore's IPmodule family.
Serial Peripheral Interface (SPI) Master Module
The SPIMmodule is part of Inicore's IPmodule family.
CAN Controller Core with 8/16 Message Objects
CANmodule-III is a full functional CAN controller module that supports the concept of mailboxes.
Infiniband 4X Link Protocol Engine
The Link Protocol Engine (LPE) is single core solution incorporating in Link Layer of Open System Interconnect (OSI) which signif…
The Gigabit Ethernet Media Access Controller is integrated Gigabit Ethernet MAC solution for Gigabit applications.
Inter-Integrated Circuit (I2C) Master Module
The Inter-IC bus, or I2C bus is a two wire serial bus.
Universal G704-E1 Framer / Deframer Core
The iniG704-E1 framer core is designed to handle synchronous frame structures (Recommondation G.704) running on E1 carrier.
High-Level Data Link Controller
Inicore's iniHDLC family of High-Level Data Link Controller (HDLC) cores consist of a Receiver (FPR: From Primary Rate) and a Tra…
Serial Peripheral Interface - Master/Slave
The DSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signa…
100M/1G/ TSN Endpoint DO-254 IP Core
AeroTSN-EP provides Time-Sensitive Networking (TSN) capabilities to devices that operate as end systems in the network.
The mesh interconnect is a scalable, high-performance communication fabric designed to connect a large number of master and slave devices in complex SoC architectures.
I2C Master/Slave Controller Core
Compatible with Philips I2C Specification version 2.1.
SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
Implements & supports MIPI SoundWire-I3S Specification
FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
AI-enhanced automation for smarter multi-die SoC and chiplet designs.
Ncore Multi-Die Interconnect IP
High-bandwidth, low-latency network-on-chip (NoC) interconnect for rapid modular innovation.
Meets the requirements of 10,000-scale XPU clusters and high performance storage
High Performance, Small Area, Low Power | Flexible Controller Configuration Solution
Supports full protocol coverage from USB 2.0 to USB 3.2 Certified by USB-IF
Silicon Library (SLI) HDMI 2.0 RX IP solution, which consists of PHY analog IP and digital LINK IP, is compliant with HDMI 2.0b standard.