Inter-Integrated Circuit (I2C) Master Module
The Inter-IC bus, or I2C bus is a two wire serial bus.
- I2C / I3C
- Proven in ASIC and FPGA Technologies
- now
- I2C-Compatible
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Inter-Integrated Circuit (I2C) Master Module
The Inter-IC bus, or I2C bus is a two wire serial bus.
Universal G704-E1 Framer / Deframer Core
The iniG704-E1 framer core is designed to handle synchronous frame structures (Recommondation G.704) running on E1 carrier.
High-Level Data Link Controller
Inicore's iniHDLC family of High-Level Data Link Controller (HDLC) cores consist of a Receiver (FPR: From Primary Rate) and a Tra…
Serial Peripheral Interface - Master/Slave
The DSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signa…
The 112G SerDes IP is a high-performance, multi-standard serializer/deserializer solution optimized for various reach profiles and advanced packaging architectures.
Peripheral Sensor Interface (PSI5) Host Controller
Configurable automotive Peripheral Sensor Interface (PSI5) host controller that implements the ECU side of PSI5 communication systems
MIPI C‑PHY/D‑PHY IP on TSMC N2P
The MXL_CSI2_RX_USL_CDPHY_ECM_T_2N2P is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the …
32 Gbps PCIe-class links, 4-tap Tx FIR, CTLE, 12-tap DFE, 30 dB IL target
1.6T Ultra Ethernet Controller
MAC/PCS/FEC Solutions up to 1.6T
Chiplet Die-to-Die Interconnect IP Solution
High Performance Chiplet Die-to-Die Interconnect Total Solution
AMBA Bus Host to eSPI Controller/Target
eSPI Controller/Target RTL SystemVerilog IP Core
AMBA Bus Host to eSPI Controller
The Digital Blocks DB-eSPI-Controller-AMBA is a fully compliant Intel Enhanced Serial Peripheral Interface (eSPI) Base Specificat…
eSPI Target RTL SystemVerilog IP Core
Enhanced Serial Peripheral Interface – Controller IP with single, dual, and quad eSPI Bus support for Intel CPU’s
Complete, reliable and fast SpaceWire encoder-decoder which has been designed according to ECSS-E-ST-50-12C.
Synopsys Verification IP (VIP) for MIPI C-Phy provides a comprehensive set of protocol, methodology, and verification features, e…
PDM Receiver/PDM-to-PCM Converter
This PDM2PCM is a configurable audio interface core that converts a mono or stereo Pulse Density Modulation (PDM) stream into sta…
TSN Ethernet Endpoint Controller 10Gbps
The TSN-EP-10G implements a configurable controller meant to ease the implementation of endpoints for networks complying with the…
Multi-channel Ultra Ethernet TSS Complete Layer
solution for UET-TSS protocol with rates up to 1.6Tbps In the data center environment, the servers, storage and AI/HPC clusters n…
Multi-channel Ultra Ethernet TSS Transform Engine
Solution for UET-TSS transform with rates up to 1.6Tbps In the data center environment, the servers, storage and AI/HPC clusters …