Vendor: Forest Semiconductor Category: Multi-Protocol PHY

DSP-Based 112G SerDes

The 112G SerDes IP is a high-performance, multi-standard serializer/deserializer solution optimized for various reach profiles and advanced packaging architectures.

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Overview

The 112G SerDes IP is a high-performance, multi-standard serializer/deserializer solution optimized for various reach profiles and advanced packaging architectures. Designed for ultra-low power, high-speed data transmission, it supports PAM-4 signaling and advanced DSP equalization across multiple technology nodes.

Data Rate Support

  • 10.3125 Gbps
  • 106.25 Gbps
  • 25.78125 Gbps
  • 53.125 Gbps
  • 112.5 Gbps
  • PCIe Gen4 / Gen5 / Gen6

Supported Reach Variants

Variant Application Scope Insertion Loss Description
VSR/ XSR Chip-to-module, chiplet interconnects ≤10 dB Ultra-low power and area optimized
MR PRBS Generator/Checker ≤20 dB Balanced performance and reach
LR/ ELR PRBS Generator/Checker 28-35 dB Advanced DSP and FEC required
Linear/ Direct Co-packed optics N/A Eliminates retimers and DSP in Optical module

Key features

  • Low power DSP architecture
  • Multi-standard protocol and multi-data-rate support
  • PAM-4 modulation with robust jitter margin
  • On-chip PRBS generator and checker
  • Advanced DSP-based adaptive equalization (FFE/DFE)
  • BER monitor and figure-of-merit tracking
  • Auto-negotiation and link training
  • Internal and e xternal loopback testing
  • Scalable lane integration and cascaded clock distribution
  • JTAG interface for debug and test
  • PAM-4 modulation with robust jitter margin

Applications

  • Chiplet-based SoC architectures
  • Co-packaged optics
  • High-speed networking (Ethernet, PCIe)
  • Data center interconnects

What’s Included?

  • Documentations
  • Model : Verilog model, IBIS-AMI models, Liberty timing views (.lib)
  • GDSII
  • LEF abstracts (.LEF) , CDL netlist (.CDL)

Specifications

Identity

Part Number
Ventana
Vendor
Forest Semiconductor
Type
Silicon IP

Provider

Contact Forest Semiconductor

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is DSP-Based 112G SerDes?

DSP-Based 112G SerDes is a Multi-Protocol PHY IP core from Forest Semiconductor listed on Semi IP Hub.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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