eSPI Controller

DESPI eSPI Controller IP Core – High-Speed, Fully Configurable eSPI Controller for FPGA and ASIC

The DESPI eSPI Controller IP Core is a fully configurable Enhanced Serial Peripheral Interface (eSPI) Controller, compliant with the eSPI Base Specification Revision 1.6. It is designed for high-performance embedded systems, enabling reliable, low-latency communication between host processors, microcontrollers, and eSPI-enabled peripheral devices, including Embedded Controllers (EC) in Intel-based platforms.

As a modern replacement for the legacy LPC (Low Pin Count) interface, the DESPI Controller IP delivers high-speed serial communication with support for single, dual, and quad SPI modes. With serial clock frequencies up to 66 MHz, it ensures efficient data transfer, reduced pin count, and improved system throughput in advanced SoC designs.

Its modular and scalable architecture allows seamless integration into FPGA and ASIC environments, making it suitable for a wide range of applications requiring robust eSPI host/controller functionality.

• eSPI Controller IP compliant with eSPI Base Specification Rev. 1.6
• Configurable Controller mode for integration into complex SoC architectures (looking for an eSPI Target? here it is)
• High-speed SPI interface up to 66 MHz for low-latency communication
• Support for Single, Dual, and Quad SPI transfers to maximize bandwidth and performance
• Large, highly configurable shared memory buffer enables efficient and flexible frame and data storage to fit any needs.
• Customizable peripheral channels, including memory-mapped I/O, Virtual Wire signals, and event signaling
• Technology-agnostic RTL design compatible with all major FPGA and ASIC vendors
• Optimized for Intel-based systems and embedded controller communication

Compliant with eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.6

• Supports Master Mode
• Supports Single, Dual and Quad modes
• Supports TX and RX operation as per specs
• Support for
  • Command Phase
  • Turn-Around Phase
  • Response Phase
• Baud Rate selection
• Slave Triggered Transactions
• Power management Event
• Interrupts and Alerts
• In-band reset
• Support for multiple channels
  • Peripheral channel
  • Virtual wire Channel
  • OOB Message (Tunneled SMBus) Channel
  • Run-time Flash Access Channel
• Various Master/Slave errors detection
• CRC Checking and generation
• The simple interface allows easy connection to microcontrollers
• Fully synthesizable, static synchronous design with no internal tri-states

Available system interface wrappers:

• AMBA – APB / AHB / AXI Bus
• Altera Avalon Bus
• Xilinx OPB Bus

• Host interface for Embedded Controllers (EC) in Intel CPU platforms
• FPGA and ASIC-based SoC designs requiring eSPI Master functionality
• High-speed data acquisition systems and industrial embedded platforms
• Multi-slave microcontroller systems with low-latency communication requirements
• Replacement of legacy LPC interfaces in modern hardware architectures