Vendor: Cadence Design Systems, Inc. Category: UALink

UALink Controller

Seamless Scale-Up for Next Generation AI

Contact Provider Request Datasheet

Overview

Scale IP Performance for Future-Ready AI Systems

Efficient scaling of AI accelerators is necessary for achieving breakthrough performance and throughput in modern compute environments. The UALink Controller, part of Cadence’s verified UALink IP subsystem, delivers ultra-low latency and high-bandwidth interconnects that enable seamless scale-up connectivity between AI accelerators. It supports memory semantics for read, write, and atomic operations, ensuring fast, coherent data handling across workloads. UALink IP provides a scalable, future-ready solution for next-generation AI infrastructure.

As a contributor member of the UALink Consortium, Cadence offers a complete UALink solution—including controller, PHY, drivers, and verification IP—optimized for both short- and long-reach applications.

Key features

  • Multi-Line Rate Support: Compatible with 100G and 200G data rates (per lane).
  • FEC Interleave Options: 1-way, 2-way, and 4-way interleave modes for latency optimization.
  • Integrated Debugging Tools: Includes flit-play for error injection and flit-capture for field diagnostics.
  • Security Enhancements: Optional secure layer integration for authentication and encryption.
  • Protocol Flexibility: Supports all 1.0 features.

Block Diagram

UALink Controller block diagram

Benefits

  • Power-Efficient Design: Engineered for optimal performance-per-watt across AI workloads.
  • Low-Latency Architecture: Minimizes communication delays for real-time responsiveness.
  • Scalability: Optimized PHY, PCS, and controller for scale-up connectivity.
  • Proven Solution: Fully verified protocol stack with controller and PHY integration.

Specifications

Identity

Part Number
UALink Controller
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Cadence Design Systems, Inc.

Learn more about UALink IP core

UALink Under the Hood: Why Full-Stack Verification Wins

Verifying UALink means following a transaction the way the silicon does: down through four layers, out across one, two, or four SerDes lanes at the configured 100G or 200G serial rate, and back again, with its meaning and its bytes both intact. This blog takes that journey one layer at a time, and along the way examines a detail of the data link flit that is easy to overlook and important to get right.

Securing Scale-Up AI: Cadence’s Complete UALink Solution

As an early contributor to the UALink ecosystem, Cadence delivers a production-ready solution built for real-world AI deployments. By combining high-performance connectivity IP with integrated security, Cadence enables customers to scale AI infrastructure with confidence.

Validating UPLI Protocol Across Topologies with Cadence UALink VIP

The UPLI (UALink Protocol Level Interface) is a logical signaling interface that facilitates communication between devices—specifically between originator devices (which initiate transactions) and completer devices (which respond to them). Each transaction comprises a request and a corresponding response, forming a complete communication cycle. Cadence UALink VIP supports various topologies to verify UPLI layer of DUT.

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

At the recent ECOC 2025 conference in Copenhagen, Cadence showcased its key role in enabling the future of AI infrastructure with live silicon demonstrations of several essential IP technologies for emerging 800G and 1.6T networks. Powered by Cadence's 224G SerDes IP, Cadence's Ultra Accelerator Link (UALink 1.0) scale-up and Ultra Ethernet scale-out networking solutions deliver the performance, flexibility, and interoperability needed for next-generation AI factories and hyperscale data centers.

AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP

In this second blog of our ongoing series, we examine how Cadence, in close partnership with TSMC, helps teams accelerate AI silicon design at advanced process nodes. For customers, this translates into reduced design risk, faster convergence to tapeout‑quality results, and greater confidence at the leading edge of AI and HPC design.

Frequently asked questions about UALink IP cores

What is UALink Controller?

UALink Controller is a UALink IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this UALink?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UALink IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP