Vendor: Cadence Design Systems, Inc. Category: UALink

UALink Controller

The UALink Controller delivers ultra-low latency and high-bandwidth interconnects that enable seamless scale-up connectivity between AI accelerators

Overview

Scale IP Performance for Future-Ready AI Systems

Efficient scaling of AI accelerators is necessary for achieving breakthrough performance and throughput in modern compute environments. The UALink Controller, part of Cadence’s verified UALink IP subsystem, delivers ultra-low latency and high-bandwidth interconnects that enable seamless scale-up connectivity between AI accelerators. It supports memory semantics for read, write, and atomic operations, ensuring fast, coherent data handling across workloads. UALink IP provides a scalable, future-ready solution for next-generation AI infrastructure.

As a contributor member of the UALink Consortium, Cadence offers a complete UALink solution—including controller, PHY, drivers, and verification IP—optimized for both short- and long-reach applications.

Key features

  • Multi-Line Rate Support: Compatible with 100G and 200G data rates (per lane).
  • FEC Interleave Options: 1-way, 2-way, and 4-way interleave modes for latency optimization.
  • Integrated Debugging Tools: Includes flit-play for error injection and flit-capture for field diagnostics.
  • Security Enhancements: Optional secure layer integration for authentication and encryption.
  • Protocol Flexibility: Supports all 1.0 features.

Block Diagram

UALink Controller block diagram

Benefits

  • Power-Efficient Design: Engineered for optimal performance-per-watt across AI workloads.
  • Low-Latency Architecture: Minimizes communication delays for real-time responsiveness.
  • Scalability: Optimized PHY, PCS, and controller for scale-up connectivity.
  • Proven Solution: Fully verified protocol stack with controller and PHY integration.

Specifications

Identity

Part Number
UALink Controller
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Files

Product Sheet Download

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Provider

Learn more about UALink IP core

PCI Express Security and TEE Integration, Part 1 - Establishing Trust

Protecting processor memory alone is no longer sufficient. The entire I/O path must become part of the trusted computing architecture. To address this challenge, PCI-SIG® has developed a suite of complementary security technologies, including Data Object Exchange (DOE), Component Measurement and Authentication (CMA), Integrity and Data Encryption (IDE), and the TEE Device Interface Security Protocol (TDISP).

How a Multi-Protocol PHY Simplifies Physical AI Connectivity

Physical AI systems must move large amounts of data across two very different connectivity domains. Accelerators and local storage need high-bandwidth, low-latency links close to the compute SoC, while sensors and control modules require reliable connectivity across the larger platform. Supporting both domains with separate high-speed PHYs can increase silicon area and integration complexity.

Frequently asked questions about UALink IP cores

What is UALink Controller?

UALink Controller is a UALink IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this UALink?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UALink IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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