Peripheral Sensor Interface (PSI5) Host Controller
Configurable automotive Peripheral Sensor Interface (PSI5) host controller that implements the ECU side of PSI5 communication systems
Overview
The PSI5-HOST IP core is a configurable automotive Peripheral Sensor Interface (PSI5) host controller that implements the ECU side of PSI5 communication systems. The core supports PSI5 Specification v2.3 and is backward compatible with PSI5 v1.3.
PSI5-HOST enables robust communication between ECUs and automotive sensors using low-cost two-wire communication over sensor power lines.
The core supports both synchronous and asynchronous modes, ECU-to-sensor downstream communication using tooth-gap or pulse-width encoding, and sensor-to-ECU Manchester-coded upstream messaging.
The PSI5-HOST architecture incorporates several safety-oriented features, including programmable watchdog timing slots monitoring, receive frame timestamps, and data protection using CRC or parity according to the PSI5 specification. These features allow smooth PSI5-HOST integration into ISO 26262-oriented automotive systems.
Access to the PSI5-HOST registers is provided through an AMBA APB register interface. The silicon-proven PSI5-HOST core is designed to industry best practices and has been rigorously verified. Optional functional safety documents and dedicated diagnostic features help developers integrate the core into ISO 26262 safety-related automotive designs.
Key features
Supported Protocols and Modes
- PSI5 v2.3 and PSI5 v1.3 protocols
- 125kbps and 189kbps upstream modes
- Synchronous and asynchronous communication
PSI5 Transmission
- Configurable support for up to 8 independent PSI5 channels
- Up to 6 timing slots per channel
- Support for both 125kbps and 189kbps upstream modes per different channels at a time
- Tooth-gap or pulse-width mode downstream communication
- Manchester decoding and error detection
Safety Oriented Features
- Parity-protected control/status registers and data buffer
- Programmable glitch filters, CRC, and parity handling
- Receive data slot timing monitor (Watchdog)
- 24-bit timestamp generation with internal or external time base
- Programmable RX glitch filter
Configurable Receive Data Memory
- Off-core SRAM or internal, flop-based design options
- Up to 32 receive frames per channel, pre-synthesis configurable
- One common memory block, shared between all implemented channels
- Can operate as FIFOs or random access buffers
Host Integration and Control Interfaces
- APB2/APB3/APB4/APB5 configurable CSR interface
- Low-power operation with clock gating
- Configurable number of Trigger IOs
- Programmable interrupt architecture
Block Diagram
What’s Included?
- Verilog RTL source code, or targeted FPGA netlist
- Simulation and Synthesis scripts
- Comprehensive user documentation and IP-XACT register descriptions
- Options:
- UVM Testbench
- ISO 26262 ASIL-D certification package, comprising a Safety Manual (SAM) and FMEDA documents
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about SENT IP cores
What is Peripheral Sensor Interface (PSI5) Host Controller?
Peripheral Sensor Interface (PSI5) Host Controller is a SENT IP core from CAST listed on Semi IP Hub.
How should engineers evaluate this SENT?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SENT IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.