ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools
Standards-compliant IP supports CAN XL tools and deterministic Ethernet switches for OEM R&D, production, and testing
Vendor:
CAST
Category:
SENT
Peripheral Sensor Interface (PSI5) Host Controller
Configurable automotive Peripheral Sensor Interface (PSI5) host controller that implements the ECU side of PSI5 communication systems
Overview
The PSI5-HOST IP core is a configurable automotive Peripheral Sensor Interface (PSI5) host controller that implements the ECU side of PSI5 communication systems. The core supports PSI5 Specification v2.3 and is backward compatible with PSI5 v1.3.
PSI5-HOST enables robust communication between ECUs and automotive sensors using low-cost two-wire communication over sensor power lines.
The core supports both synchronous and asynchronous modes, ECU-to-sensor downstream communication using tooth-gap or pulse-width encoding, and sensor-to-ECU Manchester-coded upstream messaging.
The PSI5-HOST architecture incorporates several safety-oriented features, including programmable watchdog timing slots monitoring, receive frame timestamps, and data protection using CRC or parity according to the PSI5 specification. These features allow smooth PSI5-HOST integration into ISO 26262-oriented automotive systems.
Access to the PSI5-HOST registers is provided through an AMBA APB register interface. The silicon-proven PSI5-HOST core is designed to industry best practices and has been rigorously verified. Optional functional safety documents and dedicated diagnostic features help developers integrate the core into ISO 26262 safety-related automotive designs.
Key features
Supported Protocols and Modes
- PSI5 v2.3 and PSI5 v1.3 protocols
- 125kbps and 189kbps upstream modes
- Synchronous and asynchronous communication
PSI5 Transmission
- Configurable support for up to 8 independent PSI5 channels
- Up to 6 timing slots per channel
- Support for both 125kbps and 189kbps upstream modes per different channels at a time
- Tooth-gap or pulse-width mode downstream communication
- Manchester decoding and error detection
Safety Oriented Features
- Parity-protected control/status registers and data buffer
- Programmable glitch filters, CRC, and parity handling
- Receive data slot timing monitor (Watchdog)
- 24-bit timestamp generation with internal or external time base
- Programmable RX glitch filter
Configurable Receive Data Memory
- Off-core SRAM or internal, flop-based design options
- Up to 32 receive frames per channel, pre-synthesis configurable
- One common memory block, shared between all implemented channels
- Can operate as FIFOs or random access buffers
Host Integration and Control Interfaces
- APB2/APB3/APB4/APB5 configurable CSR interface
- Low-power operation with clock gating
- Configurable number of Trigger IOs
- Programmable interrupt architecture
Block Diagram
Click to open fullscreen
What’s Included?
- Verilog RTL source code, or targeted FPGA netlist
- Simulation and Synthesis scripts
- Comprehensive user documentation and IP-XACT register descriptions
- Options:
- UVM Testbench
- ISO 26262 ASIL-D certification package, comprising a Safety Manual (SAM) and FMEDA documents
Specifications
Identity
Part Number
PSI5-HOST
Vendor
CAST
Type
Silicon IP
Application
Automotive
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about SENT IP core
Bridging the MACsec Gap: Add Line-Rate Security Without Redesigning Your Ethernet Subsystem
Now place a MACsec engine between an existing MAC and PHY with new xMII bridges; handle key management with new MKA stack and drivers
Single Pair Ethernet and TSN: The In-Robot Network Behind the Next Humanoid Robots
Humanoid robots are moving from research demos toward real products, and the network inside them is becoming the hard problem. Single Pair Ethernet and Time-Sensitive Networking are emerging as the answer, and CAST already builds the IP cores that make it deterministic.
CAST Introduces 100 Gbps TCP/IP Hardware Stack IP Core for High-Performance ASIC and FPGA Designs
Autonomous hardware TCP/IP stack delivers reliable, high-throughput, low-latency networking for AI and HPC clusters, hyperscale data centers, SmartNICs, and NVMe-over-TCP systems
CAST Enhances Serial Memory Controller IP with Encryption, Low-Power, and ASIL-Ready Options
Production-proven xSPI, HyperBus, and Xccela controller adds AES encryption, AMBA® power-state management, and programmable delay tuning
Moving to AMBA® 5? Your AMBA® 4 IP Can Still Come With You
As SoC architectures adopt AMBA® 5 fabrics and components, many proven IP blocks still rely on AMBA® 4 or earlier interfaces. That creates a common integration problem: how do designers connect newer AMBA® 5 system components to existing IP without redesigning the IP or replacing verified blocks?
Frequently asked questions about SENT IP cores
What is Peripheral Sensor Interface (PSI5) Host Controller?
Peripheral Sensor Interface (PSI5) Host Controller is a SENT IP core from CAST listed on Semi IP Hub.
How should engineers evaluate this SENT?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SENT IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.