The best of both worlds: Optimizing OCP slave memory behavior
This paper discusses how DesignWare VIP for OCP helps you test the spread of best-case, worst-case memory response.
Vendor:
Synopsys, Inc.
Category:
Bus Fabric
Verification IP for AMBA AXI4-Stream
Synopsys Verification IP (VIP) for Arm® AMBA® AXI4-Stream™ provides a comprehensive set of protocol, methodology, verification, a…
Overview
Synopsys Verification IP (VIP) for Arm® AMBA® AXI4-Stream™ provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of Arm AMBA-based designs supporting AXI4-Stream.
Key features
- Includes Master, Slave, Monitor
- Ability to control wait states and slave response types
- Ability to control signal values during idle periods
Block Diagram
Verification IP for AMBA AXI4-Stream block diagram
Benefits
- Native SystemVerilog/Verilog with UVM
- Runs natively on all major simulators
- Reference Verification Platform
- Built-in verification plan and coverage
- Verdi® protocol aware debug
- Debug port for transaction tracking on waveforms
Specifications
Identity
Part Number
Verification IP for AMBA AXI4-Stream
Vendor
Synopsys, Inc.
Type
Verification IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about On-Chip Bus IP cores
What is Verification IP for AMBA AXI4-Stream?
Verification IP for AMBA AXI4-Stream is a Bus Fabric IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this Bus Fabric?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Bus Fabric IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.