The LVDS implements LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface.
- Single-Protocol PHY
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The LVDS implements LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface.
PCIe 5.0/4.0/3.0 PHY & Controller
The PCIe 5.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 5.0/4.0/3.0, and PIPE specific…
The AXI4-DMA IP core implements a Direct Memory Access (DMA) engine that efficiently moves data between AXI4-Stream peripherals a…
The 32G SerDes PHY is a configurable IP solution capable of supporting data rates of up to 32 Gbps per lane.
The 64G SerDes PHY is a configurable PHY capable of supporting speeds up to 64Gbps within a single lane.
The Compute Express Link® (CXL®) 3.1 Controller is a parameterizable design for ASIC and FPGA implementations.
Low-power, long-reach, multi-protocol PHY for PCIe 4.0
The first IP for PCIe 3.1 with L1 sub-states support
Fast local memory for high-performance systems.
The Tessent Embedded Analytics NoC Monitor provides non-intrusive monitoring of interconnect activity across the AMBA 5 CHI (Cohe…
Configurable CAN Bus Controller with Flexible Data-Rate
CAN FD FULL IP Core is a missing gap between CAN FD and CAN XL.
The MIPI RFFE Master controller IP is a optimized and technology agnostic implementation of the MIPI RFFE v.3.1 standard targetin…
USB 2.0 PHY IP, Silicon Proven in TSMC 16FFC
The entire physical layer (PHY) IP solution for USB 2.0 was created to provide exceptional performance and consume little power.
High-performance, low-latency PHY for D2D connectivity
ULL TCP/IP, UDP/IP Offload Engine
High-performance TCP and UDP IP offload engine cores offer a reliable, ultra-low-latency solution for financial and network appli…
MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 55 ULP
The most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4.1 Specification, UniPro v1.8 Specific…
MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 40 LP
The MIPI M-PHY Gear 4 IP is compatible with the most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-…
MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 40 LP
Many production nodes use the C-PHY/D-PHY Combo because it uses the fewest resources and energy.
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 40 LP
C-PHY/D-PHY Combo in various production nodes at low cost and power.
MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 28 HPC+
Several production nodes employ C-PHY/D-PHY Combo to consume the least amount of energy and funds.