eDisplayPort v1.4 Transmitter Controller IP Core
This eDisplayPort 1.4 Tx Controller IP Core integrates into any SoC or FPGA development, supporting the eDisplayPort 1.4b specifi…
- Displayport
- In Production
- Immediately
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
eDisplayPort v1.4 Transmitter Controller IP Core
This eDisplayPort 1.4 Tx Controller IP Core integrates into any SoC or FPGA development, supporting the eDisplayPort 1.4b specifi…
eDisplayPort v1.4 Receiver Controller IP Core
This eDisplayPort 1.4 Rx Controller IP Core is a versatile and comprehensive solution designed for easy integration into any SoC …
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SAM 14LPP
The GPHY is a fully integrated IP Core with low power consumption for Giga 10/100/1000 Ethernet applications.
Slave side SPI/QPI controller 133MHZ
This SPI/QPI PHY IP is fully compatible with Macronix NOR Flash SPI products.
The Synopsys Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity…
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processor…
USB 3.1/DisplayPort 1.3 Controller IP Solutions
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB 3.1/DisplayPort 1.4 IP Subsystem Solution
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
MIPI C/D-PHY CSI/DSI TX and RX
The MIPI C/D-PHY + DSI/CSI Controller IP is a versatile solution designed for high-speed data transmission in mobile and multimed…
The M-PHY implements MIPI M-PHY protocol V4.1.
The LVDS implements LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface.
PCIe 5.0/4.0/3.0 PHY & Controller
The PCIe 5.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 5.0/4.0/3.0, and PIPE specific…
The AXI4-DMA IP core implements a Direct Memory Access (DMA) engine that efficiently moves data between AXI4-Stream peripherals a…
The 32G SerDes PHY is a configurable IP solution capable of supporting data rates of up to 32 Gbps per lane.
The 64G SerDes PHY is a configurable PHY capable of supporting speeds up to 64Gbps within a single lane.
The Compute Express Link® (CXL®) 3.1 Controller is a parameterizable design for ASIC and FPGA implementations.
Low-power, long-reach, multi-protocol PHY for PCIe 4.0
The first IP for PCIe 3.1 with L1 sub-states support
Fast local memory for high-performance systems.
The Tessent Embedded Analytics NoC Monitor provides non-intrusive monitoring of interconnect activity across the AMBA 5 CHI (Cohe…