MIPI D-PHY Tx IP, Silicon Proven in TSMC 40LP
The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification.
- MIPI D-PHY
- TSMC
- 40nm
- LP
- In Production
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
MIPI D-PHY Tx IP, Silicon Proven in TSMC 40LP
The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 16FFC
The MIPI D-PHY RX IP Core fully adheres to the D-PHY specification, version 1.2.
MIPI D-PHY Tx IP, Silicon Proven in TSMC 16FFC
The MIPI D-PHY Tx IP Core is fully compliant with the D-PHY specification, version 1.2, ensuring adherence to industry standards.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 12FFC
Several production nodes employ C-PHY/D-PHY Combo with the least amount of power and expense.
MIPI D-PHY Tx IP, Silicon Proven in TSMC 12FFC
C-PHY/D-PHY Combo in various process nodes with low power and cost.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 7FF
Various manufacturing nodes using C-PHY/D-PHY Combo at minimal cost and power.
MIPI D-PHY Tx IP, Silicon Proven in TSMC 7FF
Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes.
USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 55LL
The USB3.1Type-C PHY is a high-speed, SERDES IP with high performance that was created for semiconductors that allow high-bandwid…
Ethernet Real-Time Publish-Subscribe (RTPS) IP Core
The Real-Time Publish-Subscribe (RTPS) core provides a hardware IP solution for the Ethernet RTPS protocol.
USB 2.0 PHY IP, Silicon Proven in TSMC 90G
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption.
USB 2.0 PHY IP, Silicon Proven in TSMC 65LP
A physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.
USB 2.0 PHY IP, Silicon Proven in TSMC 55LP
In order to deliver great performance and use little power, the whole physical layer (PHY) IP solution for USB 2.0 was developed.
USB 2.0 PHY IP, Silicon Proven in TSMC 12FFC
The whole physical layer (PHY) IP solution for USB 2.0 was designed for outstanding performance and low power consumption.
USB 2.0 PHY IP, Silicon Proven in TSMC 7FF
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption.
USB 3.0 PHY IP, Silicon Proven in TSMC 55LP
For auxiliary devices, a Universal Serial Bus (USB) transceiver is offered.
USB 3.0 PHY IP, Silicon Proven in TSMC 40LP
A Universal Serial Bus (USB) transceiver is available for auxiliary devices.
USB 3.0 PHY IP, Silicon Proven in TSMC 22ULP
The USB 3.0 PHY IP Core is a transceiver provided for supplementary devices, compliant with UTMI (USB SuperSpeed), USB 3.0, and U…
USB 3.0 PHY IP, Silicon Proven in TSMC 16FFC
A Universal Serial Bus (USB) transceiver is available for auxiliary devices.
USB 3.0 PHY IP, Silicon Proven in TSMC 12FFC
For auxiliary devices, a Universal Serial Bus (USB) transceiver is offered.
USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 28HPC+
All USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps are supported by the USB 3.2 Gen2X1 transceiver IP.