32G SerDes

The 32G SerDes PHY is a highly configurable IP solution capable of supporting data rates of up to 32 Gbps per lane. It is designed to accommodate a wide range of high-speed SerDes protocols, including PCIe, USB, Rapid IO, XAUI, SATA, Ethernet, and JESD204B/C, through flexible PCS layer configurations and programmable register settings. The PHY is architected to support multi-lane implementations, featuring a shared common block that integrates a Tx PLL, reference clock input, bandgap, bias circuitry, and termination calibration. This common block efficiently supports up to four Tx/Rx lanes, enabling scalable and high-performance connectivity solutions.

To further streamline integration, the vendor offers a complete package solution that includes corresponding controllers. This end-to-end offering empowers customers to accelerate development cycles, ensure robust performance, and maintain a competitive edge in the rapidly evolving landscape of connectivity technologies.

• Reference Clock
  • 19.2MHz~300MHz, integer multiple of Serial output (100MHz for PCIe)
  • +/-300ppm frequency stability (<20Gbps), +/-100ppm frequency stability (>=20Gbps)
  • Supports both SRNS & SRIS modes
  • Configurable as reference clock repeater
• Internal PLL
  • Used to drive all PHY transmitters and receivers
  • LC-tank architecture operational from 16~32 Gbps, Ring PLL covering 1.0~16Gbps
  • Programmable pre-divider & feedback divider
  • Initiative SSC or reference clock based passive SSC
• Data Transmit/Receive
  • Rates supported from 1.0~32 Gbps
  • AC coupled
  • 50Ω impedance, internally calibrated
  • 200~1000mV(TX)/1200mV(RX) differential peak-peak, programmable
  • 3 tap pre/post-cursor de-emphasis, programmable
  • Programmable Rise/Fall times
  • CTLE, programmable
  • DFE, 6-tap programmable
  • CDR
• Testing
  • Scan
  • BIST with PRBS7, PRBS23 and PRBS31(PG & SD)
  • Loopback (near-end , far-end, on/off-die)
  • On-chip scope (eye height & width)
  • Analog and digital probe points
  • HTOL, IDDQ
• Interface with Controller
  • IPE4.4.1 & 32 bits data bus for PCIe and USB3.x
  • SAPIs for SATA3.0
  • XGMII for XAUI and 10GbE
  • SerDes interface for customized PCS

• Offers leading performance, power, and area per terabit
• Optional PI/SI and thermal co-design service
• Full support from IP delivery to production

• Verilog Sim Behavioral simulation model for the PHY
• Encrypted IO spice netlist for SI evaluation
• Integration Guidelines
• Test Guidelines
• GDSII Layout and layer map for foundry merge
• Place and Route LIB and LEF views for the AFE
• LVS and DRC verification reports