MIPI RFFE Master IP Core

The MIPI RFFE Master controller IP is a highly optimized and technology agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ASIC and FPGA technologies. This IP is used to connect a digital RFIC to RF front end components, like Power Amplifiers (PA), Low-Noise Amplifiers (LNA), filters, switches, power management modules, Antenna Turner and Sensors, which are considered RFFE Slaves.

It supports up to 15 slaves and 4 masters that can be connected through RFFE bus. This MIPI RFFE Master IP is backward compatible with MIPI RFFE components version 3.0, 2.1, 2.0 and 1.0.
The IP-core has been heavily tested in System Verilog random regression environment.

The MIPI RFFE Master IP core is a highly optimized Silicon Agnostic implementation of the MIPI RFFE protocol version 3.1,  used to connect a digital RFIC to RF Front end components, targeting both ASIC and FPGA’s. It delivers all features of the standard and allows for great configurability of features.

The IP support Multiple Masters on the bus with proper Bus Master Handover procedures as well as up to 15 Slave devices making it possible to build the most complex of systems.

Trigger remapping, and timed trigger operation, allow to make efficient use of the slave registers via the shadow register mechanism, coordinating the register value changes to specific points in time.

• Delivering Performance
  • Fully compliant with MIPI RFFE v3.1 Specification
  • Supports up to 15 Slaves on a single RFFE bus instance
  • Supports up to 4 Masters on a single RFFE bus instance
  • Supports all RFFE commands
  • Supports Multi-Mainfunctionality
  • Supports wide range of clock frequencies up to maximum 52 MHz
• Easy to use
  • Solid documentation including integration guide
  • Easy to use RTL test environment
  • No special software required
  • Strong engineering support for bring-up
• Robust
  • UVM based Verification
  • Lint/CDC checked
• Silicon Agnostic
  • Targeting both ASICs and FPGAs

• Test Environment
  • MIPI RFFE IP is tested in a UVM based regression environment for full functional coverage
• Silicon Agnostic
  • Designed in Verilog and targeting both ASICs and FPGAs
• Active Support
  • All support is actively provided by engineers directly

• The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
  • Solid documentation, including User Manual, Release Note and Quick Start Guide
  • Simulation Environment, including Simple Testbed, Test case, Test Script
  • Basic RTL Test Bench
  • Synthesis Scripts
  • Synopsys Lint and CDC Waivers
  • Synopsys CDC SGDC Files
  • Synopsys Constraint Files