Vendor: Arteris Category: Coherency

CodaCache Last-Level Cache IP

Fast local memory for high-performance systems.

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Overview

Fast local memory for high-performance systems.

CodaCache® addresses modern design challenges through performance-optimized caching, efficient data access, and power optimization techniques. It also effectively handles system scalability, SoC integration, timing closure, layout congestion, and real-time processing by providing scalable cache solutions, seamless integration capabilities, and support for real-time processing.

Using Arteris FlexGen, FlexNoC, FlexWay, and CodaCache IPs in the same SoC provides a unique high-performance, power-efficient, and scalable solution that meets the demanding requirements of modern SoC designs, while reducing development time, risk, and cost.

Key features

  • Flexible physical organization
  • Associativity
  • Per way configurable scratchpad memory
  • Way partitioning
  • Performance monitors
  • Performance models
  • Functional safety
  • Graphical user interface (GUI)
  • Assisted coherency management via hardware cache flush

Block Diagram

CodaCache block diagram

Benefits

Configurable systems

CodaCache configurability can fine-tune settings for optimal performance, unlocking the full potential of the cache in specific scenarios.

Increased performance

Facilitates fast and convenient access to frequently accessed data, eliminating the need to access the main memory and improving performance.

Seamless integration

AXI support results in efficient communication between components, easy integration into existing SoC designs, and accelerated development processes.

Applications

  • Automotive, Mobility, Wireless, Consumer Electronics, IoT, Server, Networking, and Industrial SoCs that require low-latency and high bandwidth Cache Coherency.

Specifications

Identity

Part Number
CodaCache
Vendor
Arteris
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Arteris
HQ: United States
Contact Arteris

Learn more about Coherency IP core

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Soft Tiling RISC-V Processor Clusters Speed Design and Reduce Risk

In system-on-chip (SoC) designs, RISC-V’s scalability becomes evident. Low-end applications might require only a single core, medium-level applications may employ a cluster of RISC-V processor cores, and high-end applications may demand an array of RISC-V clusters. However, traditional methods of manually configuring processor clusters are labor-intensive and error-prone and inhibit scalability, creating bottlenecks in design flexibility and speed. A new technique called network-on-chip (NoC) soft tiling addresses all these issues.

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Frequently asked questions about Coherency Interconnect IP cores

What is CodaCache Last-Level Cache IP?

CodaCache Last-Level Cache IP is a Coherency IP core from Arteris listed on Semi IP Hub.

How should engineers evaluate this Coherency?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Coherency IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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