The CXS Verification IP provides an effective & efficient way to verify CXS ON Chip or OFF Chip interface.
- Verification IP
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The CXS Verification IP provides an effective & efficient way to verify CXS ON Chip or OFF Chip interface.
TCP/UDP/IP Network Protocol Accelerator Platform
Accelerate Network Protocols with FPGA TCP/UDP/IP Stack The German Fraunhofer Heinrich-Hertz-Institute (HHI) has partnered with M…
The MIPI I3C Controller IP is a optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both …
The MIPI I3C Controller IP is a optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both …
The MIPI I3C Controller IP is a optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both …
USB-C 3.1/DP TX PHY for TSMC 6FF, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
USB 3.1 DisplayPort PHY - TSMC 10FF, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
USB-C 3.1/DP TX PHY for GF 22FD-SOI, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
The AXI2APB IP provides chip designers and architects, an efficient way to connect AXI & APB based IPs with reduced latency, powe…
The’s I3C (Improved Inter Integrated Circuit) is enhanced with I2C protocol and is compatible with I2C.
The AHB to APB bridge is an AHB slave, providing an interface between the highspeed AHB and the low-power APB.
I2C Dual mode IP ( master and slave mode) with APB interface to support the standard I2C Bus Protocol and APB5 Interface on the A…
PCIe 6.0 / CXL 3.0 PHY & Controller
The PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and …
PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications)
The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®) 7.0 supports all required features of the PCI Expre…
32Gbps, 31 order, Pseudo Random Bit Sequence Generator / Checker
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps.
The CAN XL IP presents a revolutionary advancement bridging the gap between CAN FD and 100Mbit Ethernet, making strides in data t…
The I3C Controller Lite is a configurable I3C controller that can be used in microcontroller-based environments to provide I3C co…
The I3C Target is a configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivity to…
The I3C Autonomous Target is intended for simple, data acquisition types of applications where a microprocessor is not needed to …
The I3C Controller is a configurable I3C controller that can be used in microcontroller-based environments to provide I3C connect…