SMIC 65nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
- USB 2.0
- SMIC
- 65nm
- LL
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
SMIC 65nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
Serial Peripheral Interface (SPI) Controller
Dolphin Technology provides Serial Peripheral Interface (SPI) IP which enables an AHB/APB host to access a serial device at high-…
The LVDS transmitter converts 28-bit data into 4-pair LVDS data stream.
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core…
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
The LVDS transceiver IP is a Serializer/Deserializer (SERDES) pair that transparently translates 12–bit parallel bus into serial …
This document describes the specifications for the General Purpose Input/Output (GPIO) core for the Processor Local Bus (PLB).
The PLBV46 Master Burst is a continuation of the Xilinx family of IBM CoreConnect compatible LogiCORE™ products.
The On-Chip Peripheral Bus (OPB) to Processor Local Bus (PLB v4.6) Bridge module translates OPB transactions into PLBV46 transact…
Virtex-6 Embedded Tri-mode Ethernet MAC Wrapper
Xilinx provides a Virtex-6 Integrated Tri-mode Ethernet MAC core with integrated serial interface to ensure first time success in…
Free LogiCORE™ IP design enabling the use of multi-gigabit transceivers for Xilinx FPGA Aurora is a LogiCORE™ IP designed to enab…
Virtex-6 Integrated Block for PCI Express (PCIe)
Xilinx provides a Virtex-6 FPGA Endpoint solutions for PCI Express® (PCIe) to configure the Virtex-6 FPGA Integrated Block for PC…
Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe)
Xilinx provides a Spartan-6 FPGA Integrated Endpoint solution for PCI Express® (PCIe) to configure the Spartan-6 FPGA Integrated …
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
32-bit/33MHz Multi-Function PCI Master/Target
The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification.
The AHB External Bus Interface (EBI) allows a CPU or AHB Master component (such as a DMA core) to transmit and receive data to an…
The Controller Area Network is a high reliable serial bus protocol defined in the Bosch CAN specification 2.0B.
HDMI 1.4 transmitter IP core is ideal for DVD, Blu-Ray Disc players, set-top boxes, A/V receivers
Analogix offers its silicon-proven HDMI IP cores (digital plus analogix PHY) for integration into customer's system-on-chip produ…