SMIC 0.18um Low Leakage MMC Card
To provide a solution of the MMC cards, SMIC18LL_MMC_04B is integrated together by three independent IPs: SMIC18LL_PRG_03, SMIC18…
- SMIC
- 180nm
- G
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
SMIC 0.18um Low Leakage MMC Card
To provide a solution of the MMC cards, SMIC18LL_MMC_04B is integrated together by three independent IPs: SMIC18LL_PRG_03, SMIC18…
SMIC 0.18um Low Leakage MMC Card
To provide a solution of the MMC cards, SMIC18LL_MMC_04 is integrated together by three independent IPs: SMIC18LL_PRG_03, SMIC18L…
SMIC 0.18um Low Leakage MMC Card
To provide a solution of MMC cards, SMIC18LL_MMC_01 is integrated together by four independent IPs: SMIC18LL_PRG_03, SMIC18LL_ROS…
The USB1.1 PHY is an IP version of USB transceiver.
SMIC 0.18um Reduced Swing Differential Signaling Transmitter
This is an embedded bus transmitter for RSDS™ (Reduced Swing Differential Signaling) interface.
650M LVDS transmitter, 5 channel
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
LVDS receiver, 650M, 5 channel
The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
The USB11PHY is an IP version of USB transceiver.
32:1 serializer followed by sub-LVDS drivers
The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data.
Sub-LVDS receiver followed by 1:4 de-serializer
The S13V25_CCP2RX _01 recovers a serial bit stream containing image data and converts it to a 4-bit 1/4 rate word.
FireLink IEEE1394b Link Layer Controller
The synthesizable IEEE1394b Link Layer Controller Core, FireLink®, is based on the Link Layer Controller that has been used for s…
The LogiCORE™ CPRI IP core is a high-performance IP solution that implements the Common Public Radio Interface (CPRI).
The Xilinx Universal Serial Bus 2.0 High Speed Device with Advance Micro controller Bus Architecture eXtensible Interface (AXI) e…
1.06/2.125/4.25 Gbps Fibre Channel and Backplane SerDes
IP
IP
Virtex-5 Endpoint Block Plus Wrapper for PCI Express (PCIe)
Xilinx provides the ability to configure the FPGA Built-in Endpoint Block for PCIe available in Virtex-5 FPGAs.
Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper
The CORE Generator™ Virtex®--5 Embedded Tri-mode Ethernet Media Access Controller (MAC) Wrapper automates the generation of HDL w…
64-bit Initiator/Target for PCI
The LogiCORE™ IP 64-bit Initiator/Target for PCI™ enables designers to build a customized 64-bit, 66 MHz system that performs at …
The logiI2S IP core from Xylon's logicBRICKS™IP library is a module for I2S audio data receiving and/or transmitting.
Configurable SPDIF-AES3 Transmitter
The SPDIF-Tx-Pro (CWda15) is a digital audio transmitter IP core supporting the SPDIF IEC60958 and AES3 standards for PCM audio a…