Tri-Rate Serial Digital Interface (SDI) Physical Layer (PHY)
Serial Digital Interface (SDI) is the most popular raw video connectivity standard used in television broadcast studios and video…
- Video Transport
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Tri-Rate Serial Digital Interface (SDI) Physical Layer (PHY)
Serial Digital Interface (SDI) is the most popular raw video connectivity standard used in television broadcast studios and video…
The SPI4 Intellectual Property (IP) core enables user instantiation of OIF-compliant System Packet Interface Level 4 Phase 2 Revi…
Multi-Rate Serial Digital Interface (SDI) PHY Layer
As the proliferation of HDTV, IPTV and VoD streaming continues, together with the increased functionality and decreasing costs of…
JEDEC Standard No.
PCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platf…
Digital Video Broadcasting - (DVB-ASI) IP Core
Digital Video Broadcasting (DVB) is a suite of open standards for digital television.
The SFI-5 Intellectual Property (IP) core enables user instantiation of an OIF-compliant SERDES Framer Interface Level 5 (SFI-5) …
Common Public Radio Interface - IP Core
This document provides technical information about the Lattice Common Public Radio Interface (CPRI) IP core.
XAUI 10Gb Ethernet Attachment Unit Interface
10Gb Ethernet Attachment Unit Interface or XAUI is a high-speed interconnect that offers reduced pin count and has the ability to…
The 2.5Gb MAC core can support data rates of 1Gbps or 2.5Gbps in LatticeSC/M™ devices.
FireCorerepresents the world’s only fully self-contained yet flexible IEEE1394 bus interface solution suite.
PLBv46 Endpoint Bridge for PCI Express
The PLBv46 Endpoint is an interface between the Processor Local Bus (PLB) and the PCI Express (PCIe®) silicon hard core.
ChipScope Integrated Bit Error Ratio Test (IBERT) for Virtex-5 GTP
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex-5 GTP is a customizable core that can be used to eva…
ChipScope Pro IBERT for Virtex-5 FPGA GTX Transceivers
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-5 FPGA GTX transceivers is a customizable core that…
ChipScope Pro IBERT for Virtex-6 FPGA GTX Transceivers
The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTX transceivers can be used to ev…
ChipScope Pro IBERT for Spartan-6 GTP Transceivers
The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for the Spartan®-6 GTP transceiver is a customizable …
The Xilinx DisplayPort® solutions include DisplayPort LogiCORE™ and DisplayPort TX and RX subsystems.
Xilinx provides a no charge Dune Network compliant RXAUI core to ensure first time success in your design.
10 Gigabit Ethernet PCS/PMA (10GBASE-R)
Included at no additional charge with Vivado® software Xilinx provides the 10 Gigabit Ethernet PCS/PMA (10GBASE-R) IP core with i…
IBM 65nm Mini-LVDS Transmitter
The Mini-LVDS transmitter converts up to 64-bit CMOS data into 16-pairs of Mini-LVDS data stream that can support Single-Link tra…