The Flexibilis Redundant Switch (FRS) is a triple-speed (10Mbps/100Mbps/1Gbps) Ethernet Layer-2 switch that supports new protocol…
- Ethernet
- Now
- Compatible with IEC 62439-3…
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The Flexibilis Redundant Switch (FRS) is a triple-speed (10Mbps/100Mbps/1Gbps) Ethernet Layer-2 switch that supports new protocol…
The Processor Local Bus (PLB v4.6) to AMBA® ( Microcontroller Bus Architecture) eXtensible Interface (AXI) Bridge translates PLBV…
The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite interface connects to the Microcontroller Bus Archit…
The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA® (Advance Microcontroller Bus Architecture)…
The LogiCORE® IP AXI Slave Burst is an interface between the AXI4 memory-mapped interface to the IPIC (IP Inter Connect).
The Microcontroller Bus Architecture (AMBA®) eXtensible Interface (AXI4) to Processor Local Bus (PLB v4.6) Bridge translates AXI …
This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterizat…
The AXI GPIO provides a general purpose input/output interface to the AXI ( eXtensible Interface) interface.
The AXI Ethernet Lite MAC supports the IEEE Std.
The axi2axi_connector is a utility module for use in EDK to cascade two AXI Interconnect modules.
The AXI ( eXtensible Interface) to APB ( Peripheral Bus) Bridge translates AXI4-Lite transactions into APB transactions.
Triple-Rate SDI on Virtex-6 FPGAs
The Serial Digital Interface (SDI), is widely used in broadcast applications for the transport of uncompressed SD and HD digital …
10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR)
The LogiCORE, 10 Gigabit Ethernet backpane PCS/PMA (10GBASE-KR) has been bundled with the 10G/25G Ethernet PCS/PMA with FEC/Auto-…
Xilinx Interlaken IP core is based on Sarance Technologies Best-In-Class Intellectual Property Interlaken is a scalable chip-to-c…
4 channel SERDES operating at up to 6.25Gbps for XAUI, RXAUI and SGMII (40nm TSMC)
PSI6254XRX is a 4 channel SERDES capable of providing XAUI (10G Attachment Unit Interface), RXAUI (10G Reduced Attachment Unit In…
Multi Protocol SERDES operating at up to 12.5Gbps (40nm TSMC)
PSI1250MP is a multi-protocol SERDES capable of operating at up to 12.5Gbps.
SMIC 65nm Low Leakage LVDS Receiver
The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core…
DisplayPort and HDMI Transmit technologies are complex mixed signal designs which require both high performance analog design (eq…
The DisplayPort Transmistter IP core is fully compliant with DisplayPort 1.1a with HDCP content protection specifications.
The MIPI M-PHY is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY.