Overview
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex-5 GTP is a customizable core that can be used to evaluate and monitor the health of Virtex-5 GTP Transceivers. The design includes pattern generators and checkers implemented in FPGA logic, as well as access to the ports and DRP attributes of the MGTs. Communication logic is also included, to allow the design to be runtime accessible through JTAG. The IBERT core is a self-contained design, and when it is generated, will run through the entire implementation flow, including bitstream generation.
Learn more about Test / Debug IP core
AMD (NASDAQ: AMD) today announced that it has received approval from all necessary authorities to proceed with the acquisition of Xilinx, Inc. (NASDAQ: XLNX).
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