Our 6th generation DisplayPort Transmitter Link Controller core supports DisplayPort 2.1, DisplayPort 1.4a and embedded DisplayPo…
- Displayport
- In Production
- Immediate
- DisplayPort 1.4, eDP 1.4a, …
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Our 6th generation DisplayPort Transmitter Link Controller core supports DisplayPort 2.1, DisplayPort 1.4a and embedded DisplayPo…
The GRSPWROUTER IP core is a VHDL model of a SpaceWire routing switch as defined in the ECSS-E-ST-50-12C standard.
FireGate is a synthesizable IEEE-1394-2008 Beta PHY core and is architected to support data rates of S100 through S3200.
Mil-Std-1553B/AS15531 Interface
The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote …
The MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI®…
The LVDS_RX is CMOS differential line receivers designed for applications requiring ultra low power dissipation, low noise, and h…
The LVDS_TX is CMOS differential line transmitter designed for applications requiring ultra low power dissipation, low noise, and…
Quad SPI Flash Memory Controller
The SPI-MEM-CTRL core is an SPI serial NOR and serial NAND flash memory controller, supporting Single, Dual and Quad I/O SPI acce…
Serializer 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
PMCC_SER12G is a macro-block designed for robust 8.5-11.3Gb/s data 32:1 serialization independent on data coding.
Deserializer 1:32 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
PMCC_DSER12G is a macro-block designed for robust data/clock recovery and demultiplexing 1:32.
Noesis Technologies ntE1_G704 Framer/Deframer is designed for E1 networks and is compliant with ITU recommendations G.704, G.706,…
Certified USB 5G & 10G Host Controller
USB 5G, 10G Host controller is a configurable core and implements the USB Host functionality that can be interfaced with third pa…
Certified USB 5G & 10G, USB2 Hub controller
USB 5G, 10G and 2.0 Hub controller is a configurable core and implements the USB Hub functionality that can be interfaced with th…
Dual FPD-link Transmitter, 24 Bits Color, 20-170 Mhz (SVGA/UXGAW/Full HDTV)
Now available up to 170 Mhz per channel !
Single Channel HDLC Controller
Noesis Technologies ntHDLC single channel High-Level Data Link Controller (HDLC) is a full-duplex transceiver with independent tr…
Full-featured Async/Clocked Serial channel
Full-featured asyn/hdlc serial channel
10Base-T Interface - requires no PHY
Full support for 10Base-T, full- or half-duplex
APB General Purpose IO (w/ interrupt)
The APB GPIO is a configurable module allowing the use of up to 32 scalable I/O lines.
The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the si…