I2C Master Serial Interface Controller
The I2C_MASTER IP Core is a Philips® I2C compliant serial interface controller capable of driving a standard two-wire bus in sing…
- I2C / I3C
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
I2C Master Serial Interface Controller
The I2C_MASTER IP Core is a Philips® I2C compliant serial interface controller capable of driving a standard two-wire bus in sing…
UDP/IP – 100 GbE Protocol Hardware Stack
The DB-UDP-IP-100GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 100…
I2C Controller IP – Slave, Parameterized FIFO, AHB Bus
The DB-I2C-S-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the AMBA 2…
I2C Controller IP – Slave, Parameterized FIFO, APB Bus
The DB-I2C-S-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
I2C Controller IP – Slave, Parameterized FIFO, AXI Bus
The DB-I2C-S-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the AMBA 4…
The DB-I2C-S-SCL-CLK-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via th…
Fully compliant with the VSF (Video Services Forum) Technical Recommendation, "Transport of JPEG 2000 Broadcast profile video in …
Multi-Channel Flex DMA IP Core for PCI Express
The Multi-Channel DMA IP Core for PCI-Express is a PCIe Endpoint with multiple industry standard AXI Interfaces.
The I2C-SMBUS core implements a serial interface controller for the Inter-Integrated Circuit (I2C) bus and the System Management …
Industry , Silicon Proven, 16 Gbps per lane IP core, backed by a portfolio of verification tools, PHY interop, and hardware demos…
Our solution is a hardware implementation of media access control protocol defined by the IEEE standard.
HDMI Receiver Link IP Core supporting the standard of HDMI 1.3a, which will be quickly implemented into SoC of consumers; product…
The Serial Peripheral Interface or SPI-bus is a simple 4- wire serial communications interface used by many peripheral chips that…
UART ,is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally, identical to the TL16C450.
USB2.0 Host controller using xHCI for High Performance
GDA’s USB 2.0 Host controller is a configurable core and implements the USB 2.0 Host functionality that can be interfaced with th…
Certified USB2.0 Device Controller
GDA’s USB 2.0 Device controller is a configurable core and implements the USB 2.0 Device functionality that can be interfaced wit…
USB 1.1/2.0 full speed USB PHY
T25201 is a and high integrated USB 2.0 low speed and full speed transceiver implementing the physical layer of a USB compliant d…
Aurora-like 64b/66b @14Gbps for ALTERA Devices
REFLEX CES introduces a release at 14Gbps of its Aurora-like IP Core based on ALTERA FPGA enabling interoperability between XILIN…
LVDS transmitter - TowerJazz 0.13um
LVDS transmitter
LVDS receiver - TowerJazz 0.13um
LVDS receiver