Vendor: So-Logic Category: RapidIO

Serial RapidIO Controller

The so_ip_srio_ctrl is a soft core implementation of Serial RapidIO controller as defined in the RapidIO specification 2.2.

Overview

The so_ip_srio_ctrl is a soft core implementation of Serial RapidIO controller as defined in the RapidIO specification 2.2.

So_ip_srio_ctrl soft core is fully compliant with the RapidIO 2.2 specification, and supports 1.25, 2.5, 3.125, and 5.0 Gbit/s data transfer rates.

So_ip_srio_ctrl core implements physical, transport and link layers, as defined in the RapidIO specification. It uses Xilinx's MGT transceivers to implement physical signaling required by the RapidIO specification. For the interface with the host processor IP core uses a highly configurable user interface.

So_ip_srio_ctrl core is delivered with fully automated testbench and a complete set of tests allowing easy package validation at each stage of SoC design flow.

The so_ip_srio_ctrl design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset. The so_ip_srio_ctrl core can be evaluated using Xilinx Evaluation Platforms before purchase. This is achieved by using a time-limited demonstration bit file for the selected Xilinx evaluation platform that allows the user to connect it’s Serial RapidIO enabled device to the So-Logic's so_ip_srio_ctrl core and evaluate system performance under different transfer scenarios.

Key features

  • Fully compliant with the RapidIO specification revision 2.2,
  • Simple transaction interface with Host processor and DMA Engine,
  • Configurable FIFOs implemented by BlockRAM in both transmit and receive paths,
  • Register file containing all necessary architectural registers providing total software control of IP core,
  • Low frequency operation,
  • Supports 1.25, 2.5, 3.125 and 5.0 Gbit/s data transfer rates,
  • Supports all commands defined in the I/O Logical specification,
  • Supports Doorbell and Data message operations defined in the Message Passing Logical specification,
  • Hardware support for:
    • Clock and Data Recovery,
    • Lane Synchronization,
    • 8b/10b coding and decoding,
    • CRC generation and checking,
    • Scrambler/Descrambler,
    • Packet/Control Symbol Assembly and Deassembly.
  • Support for various Xilinx's MGT transceivers,
  • Reference design available for various Xilinx Evaluation Platfoms.

What’s Included?

  • Source code (source code license only)
    • VHDL Source Code
  • VHDL verification environment
    • Tests with reference responses
  • Technical documentation
    • Installation notes
    • HDL core specification
    • Datasheet
  • Instantiation templates
  • Reference design
  • Technical support
    • IP Core implementation support
    • Variable length maintenance
    • Delivery of IP Core updates, minor and major changes
    • Delivery of documentation updates
    • Telephone & email support

Specifications

Identity

Part Number
so_ip_srio_ctrl
Vendor
So-Logic
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

So-Logic
HQ: Austria
SO-LOGIC electronic consulting is a engineering company providing services for the development of advanced digital system solutions. All our designers have a minimum of a lot of experience in programmable logic development and PCB design. We can take your new design ideas from the concept stage, through prototype design and checkout, to full scale manufacturing. Our emphasis has been on embedded applications that use Xilinx FPGAs and CPLDs. Some of the products designed or co-developed with clients include: Real-time speech recognition system; DSP replacement with FPGAs; Video graphic interface cards; Pattern recognition for image systems; High-speed communications links for different transmission media; Back planes; Optical measurement system; Digital Signal processing with System Generator and Matlab; Video and Audio Compression; HD-SDI, AES/EBU, Video walls with LEDs; PCI cards; USB, Firewire and Rocket IOs.

Learn more about RapidIO IP core

How to pick a RapidIO switch

Designers have many different options for implementing a RapidIO interconnect. This article outlines the decision factors that designers should consider, organized by project development phases: system design, implementation, system verification, and system evolution. A last section discusses support services, which impact all stages of project development.

Tips for maximizing RapidIO

RapidIO is an open, standards-based interconnection technology for midsize and large embedded systems. It enables packet-switched, peer-to-peer connections among ASICs, DSPs, FPGAs, microprocessors, network processors and backplanes, with speeds of up to

Frequently asked questions about RapidIO IP cores

What is Serial RapidIO Controller?

Serial RapidIO Controller is a RapidIO IP core from So-Logic listed on Semi IP Hub.

How should engineers evaluate this RapidIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this RapidIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP