SPI Master - EEPROM Controller
The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI sla…
- SPI / QSPI XSPI
- Now
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
SPI Master - EEPROM Controller
The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI sla…
The MI2CS macro implements a synchronous single-chip I2C Slave Macro capable of linking one CPU to one I2C-bus.
The MI2CM macro implements a synchronous single-chip I2C Master only Macro capable of linking one CPU to one I2C-bus.
The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus.
ARINC 429 Synchronous Transmitter Receiver
The M429T1R1 macro implements a synchronous single-chip ARINC 429 Transmit and Receive Controller Macro capable of linking one CP…
Serial protocol Interface Slave
The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master.
Universal Asynchronous Receiver Transmitter
The macro M16450, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a mic…
The FlexRay Controller fully complies with FlexRay Communication System Protocol Specification, Version 2.1, Revision A.
Serial ATA (SATA) PHY Transceiver IP
SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling.
Protocol controller IP for CAN / CAN FD
The M_CAN module is the new CAN Communication Controller IP-module that can be integrated as stand-alone device or as part of an …
Quad 3.125/6.25 Gbps Backplane SerDes
IP
Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core
TRC3002CSA is a Dual Serial ATA (SATA) PHY core for interfacing serial data between Storage Device and external 2-port PHY.
SMIC 0.18um LVDS Transceiver/Receiver
This transmitter provides CMOS signal to LVDS, and the receiver provides LVDS signal to CMOS.
PCI Express PIPE PHY Transceiver
SMS5000 is a fully integrated CMOS transceiver that handles the full Physical Layer PCI Express protocol and signaling.
This VME64 slave controller is designed for custom integration using standard FPGA and ASIC technologies.
The USB 1.1 Hub core is designed for flexibility and ease of use and is technology independent.
Rapid IO - Physical Layer Interface Core
The RapidIO™ is a packet - switched interconnect intended primarily as an intra - system interfaces for a chip-to-chip and board-…
7990 Local Area Network Controller
The SI79C90 Local Area Network Controller for Ethernet is an IP core designed to greatly simplify interfacing a microcomputer or …
The USB2.0 function controller is a integrated USB solution for USB applications.
IEEE 1394a - 2000 Link Layer Controller
The Link core is a functional block available for insertion into a customer's ASIC design, which supports the IEEE 1394a - 2000 D…