AMBA 5 AHB Bus TFT LCD / OLED Display Controller

The Digital Blocks DB9000AHB5 Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 5 AHB bus fabric to a TFT LCD or OLED display panel. It is the DB9000AHB-Lite core re-based on the AMBA 5 AHB protocol, for SoCs and FPGA subsystems whose fabric has moved from AMBA 3 AHB-Lite to AMBA 5 AHB.

AMBA 5 AHB is defined as a base protocol plus a set of optional properties, and the DB9000AHB5 follows that model: each property below is an independent synthesis option. With every optional property disabled the master and slave ports present the AHB-Lite signal set, so the DB9000AHB5 drops into an existing AHB-Lite subsystem unchanged.

In an FPGA, ASIC or ASSP device the microprocessor is typically an ARM Cortex-M or Cortex-A class processor, and frame buffer memory is either on-chip SRAM or larger off-chip SRAM or SDRAM. Figure 1 depicts the system view of the DB9000AHB5 IP Core embedded within an integrated circuit device; the DB9000AHB5 Master Port can also connect directly to a multi-port memory controller with an AHB port interface.

AMBA 5 AHB Features

• AMBA 5 AHB Master Port for frame buffer DMA and AMBA 5 AHB Slave Port for control & status, both with the AHB Lite single-master signalling that suits a point-to-point connection to a multi-port memory controller, and multi-layer AHB interconnect where a shared fabric is used
• Wide data bus support — the AMBA 5 AHB data bus width range extends to 1024 bits, and the DB9000 master data path, Input FIFO width and pixel unpack stage are parameterized to match, so bus width is sized to the panel bandwidth rather than to the protocol
• Extended Memory Types property — the extended HPROT encoding (bufferable, modifiable / cacheable, lookup, allocate, shareable) is driven on frame buffer read bursts, so a cache-coherent AMBA 5 interconnect can classify the display's traffic correctly instead of treating it as legacy non-cacheable
• Secure Transfers property — HNONSEC is driven from a control register field, allowing the frame buffer, overlay windows and cursor buffer to reside in TrustZone-protected memory
• User Signalling property — HAUSER, HWUSER and HRUSER sideband buses of configurable width, for system specific requester identification and sideband attributes
• Exclusive Transfers property (HEXCL / HEXOKAY) and master identification (HMASTER) on the Slave Port, for register access from a multi-master system
• INCR bursts sized by the Input FIFO fill level, with the AMBA 5 AHB burst-termination rules — no early burst termination is required of the interconnect
• Each property above is an independent synthesis option; all disabled presents the AHB-Lite signal set

Display Controller Features

• Wide range of programmable display panel resolutions:
  •  Maximum programmable resolution 4096×4096, from small 320×240 panels upward
  •  Horizontal pixel resolutions from 16 to 4096 pixels in 16-pixel increments
• Programmable 1 or 2-port TFT LCD / OLED display panel interface:
  •  18-bit digital (6 bits/color) and 24-bit digital (8 bits/color) parallel RGB
  • Interfaces to LVDS, DVI, HDMI and DisplayPort transmitters
• Programmable frame buffer bits-per-pixel (bpp) color depths:
  • 1, 2, 4, 8 bpp mapped through the Color Palette
  • 16, 18, 24 bpp driving the panel directly (30 bpp with the HDR option)
  • Programmable output format: RGB 6:6:6 / 5:6:5 / 5:5:5 on the 18-bit interface, RGB 8:8:8 on the 24-bit interface
• Color Palette RAM to reduce frame buffer storage and bus bandwidth:
  • 256-entry × 16-bit RAM, implemented as 128 entries × 32 bits
  • Loaded through the Slave Port statically by the microprocessor, or through the Master Port dynamically each frame by the DMA controller
• Programmable horizontal and vertical timing parameters — front porch, back porch, sync width, pixels-per-line, lines per-panel, and sync polarity
• Programmable pixel clock — divider from 1 to 128 of the bus clock, programmable polarity, or direct drive from an external pixel clock
• Programmable Data Enable timing signal, derived from the horizontal and vertical timing parameters, with programmable polarity
• AMBA 5 AHB interconnect:
  •  AMBA 5 AHB Master Port for DMA access of frame buffer memory
  •  AMBA 5 AHB (or APB) Slave Port for the control & status interface to the microprocessor
  •  Master bus data width configurable to match the memory subsystem
• Three memories:
  • Input FIFO decoupling the bus clock from the panel pixel clock, integrated with the DMA controller
  • 256-word × 16-bit Color Palette RAM
  • Output FIFO
  • FIFOs parameterizable in depth and width
• Power up and down sequencing support, with PWM backlight control
• 9 sources of internal interrupts with masking control
• Little-endian, big-endian, or Windows CE mode
• Compliance with the following specifications:
  • AMBA 5 AHB Protocol Specification
  • AMBA 3 AHB-Lite Protocol Specification v1.0, with all optional AMBA 5 properties disabled
• Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks and no internal tri-states

Display Resolution Support — Additional Information

• Example high resolutions: 1920×1200, 1920×1080, 1680×1050, 1600×1200, 1600×900, 1440×900, 1366×768, 1280×1024, 1280×768, 1024×768, 1024×600, 1024×576, 960×540, 800×600, 800×480.
• Example medium / small resolutions: 640×480, 640×400, 640×240, 640×200, 480×800, 480×640, 480×272, 480×234, 320×240, 320×200, 240×400, 240×320, 240×240.

The DB9000AHB5 is available in synthesizable RTL Verilog or technology-specific netlists for FPGAs, along with synthesis scripts, Synopsys Design Constraints (SDC), a simulation test bench with expected results, datasheet, and user manual.