Verification Sanity in Chiplets & Edge AI: Avoid the “Second Design” Trap
eFPGA integration doesn’t have to be complex. With the right approach, you can simplify verification, reduce risk, and stay on track to tape-out.
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Chiplets Semiconductor IP News & Insights
Follow the latest news, technical articles, expert perspectives and ecosystem updates related to Chiplets and semiconductor IP design.
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Rapidus Opens Analysis Center and Rapidus Chiplet Solutions
New facilities enhance Rapidus’ development environment to ensure a steady transition to mass production of cutting-edge semiconductors in 2027
Sarcina Launches UCIe-A/S Packaging IP to Accelerate Chiplet Architectures
Sarcina launches UCIe-A/S Packaging IP, enabling high-performance, scalable chiplet interconnects with reduced complexity and faster time-to-market.
Ultra Accelerator Link™ (UALink™) Consortium Publishes Four Specifications Defining In-Network Compute, Chiplets, Manageability and 200G Performance
The new specifications support the deployment of UALink solutions in multi-workload environments, while simultaneously helping improve UALink technology...
Arteris Network-on-Chip Technology Achieves Deployment Milestone of 4 Billion Chips and Chiplets
Arteris network-on-chip interconnect IP ships in production silicon at accelerating scale across AI-driven automotive, enterprise computing, consumer...
How UCIe 3.0 Redefining Chiplet Architecture: From Protocol to Platform
Explore how UCIe 3.0 is revolutionising chiplet architecture, evolving from a high-speed interconnect protocol to a unified platform that enables...
Arteris Selected by 2V Systems for IO Chiplet for Data Center
Arteris today announced that 2V Systems has licensed Arteris’ Ncore 3 cache coherent interconnect IP and Arteris’ FlexNoC 5 non-coherent interconnect...
InPsytech showcases 3nm UCIe 3.0 technology at OCP 2025, Accelerating Innovation in Chiplet Ecosystem
InPsytech has long focused on high-speed and low-power interface IP technologies. Its UCIe (Universal Chiplet Interconnect Express) portfolio supports...
UCIe™ Chiplet IP on TSMC 3DFabric® Platform
Alphawave Semi has announced the successful tape-out of its cutting edge UCIe™ 3D IP on the advanced TSMC SoIC® (SoIC-X) technology in the 3DFabric...
Analogue Insight IP Group Launches Analogue Insight SAFE in Portland, Oregon to Deliver Certification-Grade Security IP for Next-Gen SoCs and Chiplets
The new US entity will be led by Rachael J. Parker and David Johnston, expanding the Group’s global footprint alongside existing operations in the...
Alphawave Semi Delivers Cutting-Edge UCIe™ Chiplet IP on TSMC 3DFabric® Platform
By leveraging TSMC’s SoIC-X advanced 3D packaging technology, Alphawave Semi continues to push the boundaries of power, performance efficiency and...
Alphawave Semi Taped-Out Industry Leading 64Gbps UCIe™ IP on TSMC 3nm for the IP Ecosystem, Unleashing Next Generation of AI Chiplet Connectivity
Breakthrough Gen3 UCIe IP subsystem achieves 64 Gbps per-I/O pin data rates and doubles shoreline bandwidth density, enabling scalable XPUs, and...
About Chiplets in semiconductor IP
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