Andes Technology Unveils Next-Generation AI Solutions: AndesAIRE™ AnDLA™ I370 v2.0 and NN SDK v1.2.0 for Advanced ViT, VLM, and SLM at the Edge

Hsinchu, Taiwan – August 3, 2026 – Andes Technology, a leading supplier of high-performance, low-power 32/64-bit RISC-V processor cores and AI acceleration solutions, and a Founding Premier member of RISC-V International, proudly announces a major, synchronized evolutionary leap in its AI portfolio: the launch of the AndesAIRE™ AnDLA™ I370 v2.0 Deep Learning Accelerator IP and the AndesAIRE™ NN SDK v1.2.0. This milestone release addresses one of the industry’s most challenging hurdles: enabling resource-heavy Transformer architectures such as Vision Transformers (ViT), Vision-Language Models (VLMs), and Small Language Models (SLMs) to execute efficiently on power- and cost-constrained edge platforms.

Breaking Hardware Barriers: AnDLA™ I370 v2.0

To unleash the capabilities required for multimodal VLM and generative SLM workloads, the I370 v2.0 accelerator IP introduces significant architectural enhancements:

• Scalable Compute Power up to 2048 MACs: Configurable MAC arrays (spanning 32 to 2048) provide developers with the scalability needed to handle the massive matrix multiplications required by modern neural networks.
• Ultra-Wide AXI Bus up to 512 bits: Features an AXI bus data width expandable up to 512 bits, combined with enhanced DMA outstanding requests to eliminate memory bandwidth bottlenecks under heavy load.
• Multimodal VLM & Generative SLM Support: Provides native, hardware-level support for Transformer networks, powered by a Programmable Tensor Operator Set Architecture design.
• Rich Hardware-Accelerated Operators: Integrates native execution of Divider (DIV) and Square Root (SQRT) operations alongside operator fusion, ensuring complex non-linear functions run entirely within the accelerator.

Unlocking Transformer Capability: AndesAIRE™ NN SDK v1.2.0

Hardware capacity means little without sophisticated software compilation. The AndesAIRE™ NN SDK v1.2.0 serves as the critical enabler, boasting a matured toolchain specifically optimized to handle the structural complexities of Transformer networks:

• Edge Transformer Optimization: The SDK natively supports attention mechanisms, featuring an SLM prefill/decode phase split to optimize KV-cache placement and memory scheduling.
• Comprehensive Linux & RTOS Ecosystems: Extends platform flexibility with a kernel-mode driver and user-space runtime for Linux, alongside RTOS environments featuring AnDLA task preemption for latency-critical, real-time responses.
• Co-Design Tooling & Distillation: Features Model Advisor and Hardware Advisor to map the cost-performance Pareto front, paired with word-level knowledge distillation to seamlessly compress larger teacher models into AnDLA-deployable student networks.
• Upstream Framework Integration: Rebases AnDLA driver and NN Library wrapper functions onto the latest LiteRT and LiteRT for Microcontrollers AI framework. Besides, the SDK supports the MLCommons MLPerf Tiny v1.4 benchmark with outstanding performance results by integration with LiteRT for Microcontrollers (https://mlcommons.org/working-groups/benchmarks/tiny/).

“Bringing Transformer models and VLMs to cost-sensitive edge devices is arguably one of the toughest engineering problems in the current AI landscape,” said Dr. Charlie Su, CTO and President of Andes Technology. “With the I370 v2.0 enhanced with a Programmable Tensor Operator Set Architecture and backed by our NN SDK v1.2.0, we have successfully unlocked on-device transformer models. Developers can now run ViT, VLM, and SLM locally under both RTOS and Linux, paving the way for a smarter generation of edge devices.”

With these comprehensive upgrades, Andes Technology reshapes expectations for edge computing, empowering smart cameras, industrial automation, robotics, wearables, and edge gateways to process language and vision models locally. For more information regarding the AndesAIRE™ AnDLA™ I370 v2.0 and NN SDK v1.2.0, please visit www.andestech.com or contact sales@andestech.com.

Explore Andes IP:

• RVA23, Multi-cluster, Hypervisor and Android
• 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux

About Andes Technology

As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 20 billion Andes-powered SoCs are driving innovations globally. Discover more at www.andestech.com.