RISC-V: Spanning Datacenter to Edge
By Oliver Jones, CEO, Aion Silicon
As SoC architectures evolve under pressure from AI workloads, power constraints, and a continual need for differentiation, RISC-V is rapidly becoming the go-to flexible foundation spanning hyperscale datacenters to ultra-efficient edge devices. This presentation will include new industry data on RISC-V and provide a look at how companies across regions and industries are deploying RISC-V solutions. This is illustrated by real-world examples from Aion Silicon’s work including datacenter AI accelerators and host CPUs to edge AI platforms, embedded processors, and microcontrollers entering volume production.
Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
Related Videos
- Scaling AI from Edge to Data Center with SiFive RISC-V Vectors
- Paving the Road to Datacenter-Scale RISC-V
- Arm: Scaling AI Compute from Edge to Cloud
- Bringing High-Performance RISC-V Platforms to Life