Vendor:
ElectraIC
Category:
Post Quantum
PQC HW/SW IP Core
Composed of three dedicated HW IP cores (PolyCore, KeccakCore, MaskCore) and the software stack
Overview
PQC HW/SW IP Suite is composed of three dedicated HW IP cores (PolyCore, KeccakCore, MaskCore) and the software stack leveraging these IP cores to implement PQC algorithms. It is designed to support NIST’s selected Post-Quantum Cryptography (PQC) standards, ML-KEM (Kyber), ML-DSA (Dilithium), SLH-DSA (SPHINCS+), and FN-DSA (Falcon). This IP is fully compliant with the NIST’s published standards, and offers countermeasures against Side-Channel Analysis attacks.
Key features
- PQC hardware IP core set is customizable, and the standard offering includes three cores targeting PQC algorithms:
- KeccakCore, PolyCore, MaskCore
- Supported Algorithms (algorithm set is customizable):
- ML-KEM
- FIPS-203 compliant
- Key Generation, Encapsulation, Decapsulation
- All security levels: ML-KEM-512, ML-KEM-768, ML-KEM-1024
- ML-DSA
- FIPS-204 compliant
- Key Generation, Signature Generation, Signature Verification
- All security levels: ML-DSA-44, ML-DSA-65, ML-DSA-87
- SLH-DSA
- FIPS-205 compliant
- Key Generation, Signature Generation, Signature Verification
- All security levels: SLH-DSA-SHAKE-128s/f, SLH-DSA-SHAKE-192s/f, SLH-DSA-SHAKE-256s/f
- FN-DSA
- Falcon Round 3 Submission compliant. Will be updated with FIPS-206 upon its publication
- Signature Verification
- All security levels: Falcon-512, Falcon-1024
- ML-KEM
- Optional Side-Channel Analysis and Fault Injection attacks countermeasures (e.g., masking)
- AXI4 interface for system integration and drivers available upon request
- Crypto-agility: Modifications to existing implementations (e.g., new countermeasures) and new algorithms can be implemented by updating the software layer
Block Diagram
Click to open fullscreen
What’s Included?
- Encrypted Netlist
- Synthesis Scripts
- Firmware (binary)
- Comprehensive Documentation
Specifications
Identity
Part Number
EIP-30010003
Vendor
ElectraIC
Type
Silicon IP
Security
Crypto Algorithm
CRYSTALS-Dilithium (ML-DSA)
,
CRYSTALS-Kyber (ML-KEM)
,
FALCON
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Turkey
Learn more about Post Quantum IP core
How to design secure SoCs Part IV: Runtime Integrity Protection
In previous articles, we gave an overview about secure SoC architectures (Part I), about the importance of key management (Part II) and secure boot (Part III) - the first line of defense. Part IV of the series focuses on runtime integrity protection, a paramount, ensuring the application remains secure even during active operation.
How to design secure SoCs Part IV: Runtime Integrity Protection
SoC designers are increasingly challenged to integrate robust security measures into their designs. Modern connected devices, such as automotive Electronic Control Units (ECUs), Internet of Things (IoT) nodes, and industrial control systems, face increasing susceptibility to cyberattacks. This escalating threat landscape underscores the critical importance of mandatory security requirements.
Nine Compelling Reasons Why Menta eFPGA Is Essential for Achieving True Crypto Agility in Your ASIC or SoC
Today’s world is already overly complicated to provide robust product security, with extremely motivated hackers creating novel threats exposing new vulnerabilities every day. But considering tomorrow’s world with the looming threat of quantum computing, expanding AI possibilities and rapidly evolving regional regulations and export control risk with severe financial penalties, this is a daunting challenge.
Providing protection against EMFI attacks
This Agile Analog blog post is focused on describing the dangers of Electromagnetic Fault Injection (EMFI) attacks and outlining the importance of EMFI sensors that are designed to provide protection.
Deploying StrongSwan on an Embedded FPGA Platform, IPsec/IKEv2 on Arty Z7 with PetaLinux and PQC
The objective of this article is to present and analyze a concrete IPsec/IKEv2 deployment on an FPGA-based embedded Linux system. Using an Arty Z7 FPGA platform with PetaLinux and StrongSwan, the focus is on system-level integration rather than protocol theory: how the IPsec stack is built and deployed, how classical and post-quantum key exchange are integrated without modifying standardized protocols, and what architectural trade-offs arise when moving cryptographic operations into programmable logic.
Frequently asked questions about Post-Quantum Cryptography IP cores
What is PQC HW/SW IP Core?
PQC HW/SW IP Core is a Post Quantum IP core from ElectraIC listed on Semi IP Hub.
How should engineers evaluate this Post Quantum?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Post Quantum IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.