PLBv46 Endpoint Bridge for PCI Express
The PLBv46 Endpoint is an interface between the Processor Local Bus (PLB) and the PCI Express (PCIe®) silicon hard core.
- Protocol Bridge
PLBv46 Endpoint Bridge for PCI Express
The PLBv46 Endpoint is an interface between the Processor Local Bus (PLB) and the PCI Express (PCIe®) silicon hard core.
The 3GPP LTE Turbo Encoder implements the turbo convolutional encoding scheme defined in the 3GPP LTE specifications.
The 3GPP LTE RACH Detector offers a flexible and optimized implementation of the RACH detection function required for 3GPP-LTE ba…
3GPP LTE Fast Fourier Transform (LTE-FFT)
The LTE FFT LogiCORE™ IP provides support for all transform point sizes defined by the 3GPP-LTE specifications, including the 153…
ChipScope Integrated Bit Error Ratio Test (IBERT) for Virtex-5 GTP
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex-5 GTP is a customizable core that can be used to eva…
ChipScope Pro IBERT for Virtex-5 FPGA GTX Transceivers
The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-5 FPGA GTX transceivers is a customizable core that…
ChipScope Pro IBERT for Virtex-6 FPGA GTX Transceivers
The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTX transceivers can be used to ev…
ChipScope Pro IBERT for Spartan-6 GTP Transceivers
The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for the Spartan®-6 GTP transceiver is a customizable …
The Xilinx DisplayPort® solutions include DisplayPort LogiCORE™ and DisplayPort TX and RX subsystems.
Peak Cancellation Crest Factor Reduction (PC-CFR)
Xilinx provides a CFR solution for common wireless standards that is low cost, flexible, low power and solves your time to market…
Xilinx provides a DUC/DDC solution for LTE, TD-SCDMA and WCDMA that is low cost, low power and solves your time to market needs.
The Xilinx LogiCORE™ DSP48 Macro provides an easy-to-use interface that abstracts the DSP48 slice and simplifies its dynamic oper…
Xilinx provides a Video DMA core for high performance DMA memory access in video processing systems.
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
Xilinx provides a no charge Dune Network compliant RXAUI core to ensure first time success in your design.
10 Gigabit Ethernet PCS/PMA (10GBASE-R)
Included at no additional charge with Vivado® software Xilinx provides the 10 Gigabit Ethernet PCS/PMA (10GBASE-R) IP core with i…
The XPS PS2 Controller is a PLB (Processor Local Bus) slave that is designed to control PS2 devices such as keyboard and mouse.
The In System Flash (ISF) is type of serial flash memory and it is present only on the Spartan™-3AN devices.
In a multi processor environment the processors share common resources.