Xilinx, Inc. IP Cores

XPS Mailbox features a bi-directional communication channel between two processors.

• System Controller

This core allows memory mapped access to a LocalLink interface.

• FIFO / CAM

The XPS HWICAP (Hardware ICAP) IP enables an embedded microprocessor, such as the MicroBlaze™ or PowerPC™ to read and write the F…

• System Controller

This document provides the design specification for the Xilinx MicroBlaze Trace Core (XMTC), which provides instruction and data …

• Debug Trace

The XPS Thin Film Transistor (TFT) controller is a hardware display controller IP core capable of displaying 256k colors.

• Display Controller

The XPS Timer/Counter is a 32-bit timer module that attaches to the PLB bus.

• Timers & Watchdogs

The XPS Timebase Watchdog Timer Interface is a 32-bit peripheral that connects to the PLB (Processor Local Bus) and provides the …

• Timers & Watchdogs

The XPS SYSMON ADC IP Core is a 32-bit slave peripheral that connects to the PLB (Processor Local Bus) and provides the controlle…

• ADC

The XPS Interrupt Controller (XPS INTC) concentrates multiple interrupt inputs from peripheral devices to a single interrupt outp…

• Interrupt Controller

This document describes the specifications for the General Purpose Input/Output (GPIO) core for the Processor Local Bus (PLB).

• GPIO

This specification defines the architecture and interface requirements for the External Peripheral Controller (EPC).

• System Controller

Digital to analog converter (DAC) converts a binary number into a voltage directly proportional to the value of the binary number.

• DAC

The analog to digital conversion is realized in the XPS Delta-Sigma ADC (XPS ADC) using Delta-Sigma conversion technique.

• ADC

The XPS System ACE Interface Controller (or, interchangeably, the XPS SYSACE) is the interface between the Processor Local Bus (P…

• Controller

The Xilinx Multi-Channel External Memory Controller (XPS MCH EMC) provides the control interface for external synchronous, asynch…

• Controller

The XPS Central DMA Controller provides simple Direct Memory Access (DMA) services to peripherals and memory devices on the PLB.

• DMA

The XPS BRAM Interface Controller is a Xilinx IP module that incorporates a PLB V4.6 (Processor Local Bus) interface.

• System Controller

MPMC is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2 memory.

• Controller
• DDR2

The MMCM primitive in Virtex®-6 parts is used to generate multiple clocks with defined phase and frequency relationships to a giv…

• PLL

The PLBV46 Master Burst is a continuation of the Xilinx family of IBM CoreConnect compatible LogiCORE™ products.

• Protocol Bridge