Designing DDR3 SDRAM controllers with today's FPGAs
This article outlines the major differences between DDR3 and DDR2 SDRAM architecture and reviews them in the context of an FPGA-based reference design tested in hardware at 800 Mbps.
Vendor:
Xilinx, Inc.
Category:
Video Processing
Image Enhancement
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
Overview
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs. For all new designs, users are recommended to use Video Processing Subsystem.
Key features
- Performs image noise reduction
- Performs image edge enhancement
- Optional anti-halo and anti-aliasing for edge enhancement post-processing
- Support for two architectures:
- High Performance
- Minimal Resources
- YCbCr 4:4:4 and 4:2:2 input and output
- AXI4-Stream data interfaces
- Optional AXI4-Lite control interface
- Supports 8, 10, and 12-bits per color component input and output
- Built-in, optional bypass and test-pattern generator mode
- Built-in, optional throughput monitors
- Supports spatial resolutions from 32x32 up to 7680x7680
- Supports 1080P60 in all supported device families
- Supports 4kx2k @ 24 Hz in supported high performance devices
Specifications
Identity
Part Number
EF-DI-IMG-ENHANCE-SITE
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Video Processing IP
What is Image Enhancement?
Image Enhancement is a Video Processing IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this Video Processing?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.