Xilinx, Inc. IP Cores

The Adder/Subtracter IP provides LUT and single DSP48 slice add/sub implementations.

• Arithmetic Units

The TEMAC core is ideally suited for the development of high density Gigabit Ethernet communications and storage equipment.

• Ethernet

For UltraScale and UltraScale+ device support, refer to the 10G/25G Ethernet Subsystem Designed to the IEEE 802.3-2012 specificat…

• Ethernet

The Accumulator IP provides LUT and single DSP48 slice accumulation implementations.

• Arithmetic Units

The NVMe-Over-Fabrics (NVM-oF) reference platform is implemented on the Fidus Sidewinder card which supports up to 4 NVMe SSDs, a…

• NVMe Controller

Utility for instantiating various buffers, suchs as BUFG and differential IO buffers, in Vivado IP Integrator.

• Analog

Xilinx provided utility function to simplify design in Vivado IP Integrator.

• Test / Debug

DO-DI-PCIX64-VE rolls the Initiator/Target for PCI ™/PCI-X ™, 32-bit Initiator/Target for PCI and 64-bit Initiator/Target for PCI…

• PCI

With this core, the Xilinx Universal Serial Bus 2.0 High Speed Device provides a control interface to internal registers via a 32…

• USB

The Xilinx® LogiCORE™ IP JESD204 PHY core implements a JESD204B physical interface to simplify sharing serial transceiver channel…

• Single-Protocol PHY

The LogiCORE™ IP Serial RapidIO Gen 2 Endpoint solution, designed to RapidIO Gen 2.1 specification, comprises of a flexible and o…

• RapidIO

Included at no additional charge with ISE software Xilinx provides the AXI Datamover core which provides high throughput transfer…

• DMA

Included at no additional charge with Vivado and ISE Design Suite The AXI Interconnect IP connects one or more AXI memory-mapped …

• Network-On-Chip

Soft Error Mitigation (SEM) IP cores perform SEU detection, correction, and classification for configuration memory.

• Monitoring

The Utility IO Multiplexer module provides a multiplexing function between two IO vectors to one IO vector.

• GPIO

Included with Xilinx ISE Software The BUFT-based Multiplexer Slice IP core supports buses of up to 64 bits wide and 1 to 64 input…

• Control Logic

The LD-based Parallel Latch IP core is a latch-based data register with 1 to 64 bits width.

• Control Logic

Included with Xilinx ISE Software The BUFE-based Multiplexer Slice IP core supports buses of up to 64 bits wide and 1 to 64 input…

• Control Logic

The XPS Universal Asynchronous Receiver Transmitter (UART) Lite Interface connects to the PLB (Processor Local Bus) and provides …

• UART