Xilinx, Inc. IP Cores

The Microcontroller Bus Architecture (AMBA®) eXtensible Interface (AXI4) to Processor Local Bus (PLB v4.6) Bridge translates AXI …

• Protocol Bridge

The LogiCORE™ IP AXI Interrupt Controller (AXI INTC) core concentrates multiple interrupt inputs from peripheral devices to a sin…

• Interrupt Controller

This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterizat…

• I2C / I3C

The AXI Hardware ICAP enables an embedded microprocessor, such as MicroBlaze, to read and write the FPGA configuration memory thr…

• System Controller

The AXI GPIO provides a general purpose input/output interface to the AXI ( eXtensible Interface) interface.

• GPIO

The AXI Streaming FIFO allows memory mapped access to a AXI Streaming interface.

• FIFO / CAM

The AXI Ethernet Lite MAC supports the IEEE Std.

• Ethernet

The AXI External Peripheral Controller (AXI EPC IP Core) supports data transfers between the AXI4 Interface and external synchron…

• System Controller

The AXI EMC ( Microcontroller Bus Architecture (AMBA®) extensible Interface (AXI) External memory controller) provides the contro…

• Controller

The AXI Direct Memory Access (AXI DMA) IP provides high-bandwidth direct memory access between memory and AXI4-Stream-type target…

• DMA

The Xilinx LogiCORE™ IP AXI Central Direct Memory Access (CDMA) core is a soft Xilinx Intellectual Property (IP) core for use wit…

• DMA

The AXI BRAM Controller is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK) and Vivado™ IP Integrator…

• DMA

The axi2axi_connector is a utility module for use in EDK to cascade two AXI Interconnect modules.

• Protocol Bridge

The AXI ( eXtensible Interface) to APB ( Peripheral Bus) Bridge translates AXI4-Lite transactions into APB transactions.

• Protocol Bridge

The Serial Digital Interface (SDI), is widely used in broadcast applications for the transport of uncompressed SD and HD digital …

• Video Transport

The LogiCORE, 10 Gigabit Ethernet backpane PCS/PMA (10GBASE-KR) has been bundled with the 10G/25G Ethernet PCS/PMA with FEC/Auto-…

• Single-Protocol PHY

Xilinx Interlaken IP core is based on Sarance Technologies Best-In-Class Intellectual Property Interlaken is a scalable chip-to-c…

• Interlaken

The LTE PUCCH Receiver LogiCORE™ IP core provides the receive functionality required for the LTE Physical Uplink Control CHannel …

• Channel Coding

Xilinx provides a market DPD solution that reduces CapEx and OpEx Digital Pre-Distortion (DPD) is one of the most fundamental bui…

• Filters Transforms

The 3GPP LTE Channel Estimator LogiCORE™ IP provides an optimized channel estimation function for the Physical Uplink Shared Chan…

• Channel Coding