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Vendor:
Xilinx, Inc.
Category:
DSP Core
DSP48 Macro
The Xilinx LogiCORE™ DSP48 Macro provides an easy-to-use interface that abstracts the DSP48 slice and simplifies its dynamic oper…
Overview
The Xilinx LogiCORE™ DSP48 Macro provides an easy-to-use interface that abstracts the DSP48 slice and simplifies its dynamic operation by enabling the specification of multiple operations via a set of user defined arithmetic expressions. The specified operations are enumerated and can be selected by the user via a single port on the generated core.
The DSP48 Macro provides a simplified interface to the DSP48 slice by the abstraction of all opmode, subtract, alumode and inmode controls to a single SEL port. Further, all CE and RST controls are grouped to a single CE and SCLR port respectively. This abstraction enhances portability of HDL between device families. The DSP48 Macro supports a square latency model where additional register stages are added so all input to output paths have the same latency. The Macro supports 3 latency modes (automatic, tiered and expert). Automatic and tiered are square latency models, the difference being that auto gives fully pipelined whereas tiered allows finer control. This can be useful when utilizing the DSP48 slice as a processing engine. Alternatively, all additional pipeline stages can be removed to use the minimum of resources. The DSP48 Macro is recommended for applications that do not require the full versatility of control of the DSP48 slices and for applications where portability is a high priority.
Finally, the DSP48 Macro supports all the common instructions of the DSP48 slice while achieving maximum performance.
The DSP48 Macro provides a simplified interface to the DSP48 slice by the abstraction of all opmode, subtract, alumode and inmode controls to a single SEL port. Further, all CE and RST controls are grouped to a single CE and SCLR port respectively. This abstraction enhances portability of HDL between device families. The DSP48 Macro supports a square latency model where additional register stages are added so all input to output paths have the same latency. The Macro supports 3 latency modes (automatic, tiered and expert). Automatic and tiered are square latency models, the difference being that auto gives fully pipelined whereas tiered allows finer control. This can be useful when utilizing the DSP48 slice as a processing engine. Alternatively, all additional pipeline stages can be removed to use the minimum of resources. The DSP48 Macro is recommended for applications that do not require the full versatility of control of the DSP48 slices and for applications where portability is a high priority.
Finally, the DSP48 Macro supports all the common instructions of the DSP48 slice while achieving maximum performance.
Key features
- Simplified and abstracted interface to DSP slice enhances ease of use, code readability and portability
- Define DSP slice operation via a list of user defined arithmetic expressions
- Support for up to 64 instructions
- Supports the DSP slice pre-adder
- Configurable latency
- Support of signed, two’s complement input data
- Capability to specify optional separate clock enables and resets for each data and control path registers
Specifications
Identity
Part Number
DSP48 Macro
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about DSP Core IP core
Generate FPGA designs from M-code
You can use MATLAB M-files with the AccelChip synthesis tool to implement DSP on Xilinx FPGAs.
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Frequently asked questions about DSP Core IP cores
What is DSP48 Macro?
DSP48 Macro is a DSP Core IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this DSP Core?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DSP Core IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.