Vendor: Lattice Semiconductor Corp. Category: Channel Coding

Turbo Encoder

Turbo coding is an error correction technique widely used in the communications industry.

Overview

Turbo coding is an advanced error correction technique widely used in the communications industry. Turbo encoders and decoders are key elements in today's communication systems to achieve the best possible data reception with least possible errors. The basis of turbo coding is to introduce redundancy in the data to be transmitted through a channel. The redundant data helps to recover original data from the received data.

Lattice's Turbo Encoder IP Core is compliant with three different standards: 3GPP, 3GPP2, and CCSDS. The 3GPP and 3GPP2 standards are widely used in WCDMA and MC-CDMA applications while CCSDS is most commonly found in telemetry and space communications. Each one of these encoders is a separate entity as the interleaver and control logic for each encoder is completely different.

Lattice's Turbo Encoder core is created in conjunction with the Turbo Decoder core to provide users with a state of the art error correction technique.

Key features

  • Fully compatible with the following standards:
    • 3GPP TS 25.212 Version 4.2.0
    • 3GPP2 C.S0002-A
    • CCSDS 101.0-B-5
  • Up to 60 MHz clock speed
  • Variable input block sizes
  • User defined number of states
  • Fixed processing delay of 12 cycles for CCSDS, 10 cycles for 3GPP, and 9 cycles for 3GPP2.
  • User parameterized forward and backward polynomials
  • Programmable puncturing support
  • IP Core Package Contains
    • Data Sheet and User's Guide
    • Lattice Netlist and Secured Simulation Model
    • Behavioral Testbench

Block Diagram

TURBO-ENCO block diagram

Specifications

Identity

Part Number
TURBO-ENCO
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Channel Coding IP core

Lattice Collaborates with TI to Accelerate Edge AI for Robotics and Industrial Applications

The collaboration demonstrates a real-time AI sensor fusion architecture that integrates TI mmWave radar and camera sensors using NVIDIA Holoscan Sensor Bridge running on Lattice’s low power FPGA. The FPGA acts as a companion chip delivering synchronized sensor data directly into GPU-accessible memory to enable low-latency and robust perception for robotics and industrial edge AI applications.

Frequently asked questions about Channel Coding IP cores

What is Turbo Encoder?

Turbo Encoder is a Channel Coding IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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