Processor Architecture for High Performance Video Decode
Processor Architecture for High Performance Video Decode
Vendor:
Lattice Semiconductor Corp.
Category:
Filters Transforms
Distributed Arithmetic FIR (DA-FIR) Filter Generator
The Lattice Distributed Arithmetic Finite Impulse Response (DA-FIR) Filter Generator IP implements a configurable, multi-channel …
Overview
The Lattice Distributed Arithmetic Finite Impulse Response (DA-FIR) Filter Generator IP implements a highly configurable, multi-channel DA-FIR filter, using distributed arithmetic algorithms implemented in FPGA Look Up Table (LUT) or Embedded Block Memory (EBR) to efficiently support the sum-of-product calculations required to perform the filter function. These techniques generate very area-efficient utilization of the FPGA LUTs while enabling savings of multiply-accumulate blocks (sysDSP) for other design logic. As a result, the DA-FIR Filter Generator IP core is extremely useful for implementing custom DSP blocks in Lattice FPGAs. Please refer to the user's guide to determine which cores are available for each device family.
Key features
- Variable number of taps up to 1024
- Multi-channel support (up to 32 channels)
- Polyphase interpolation/decimation filters
- Halfband filters
- Interpolation and Decimation ratios from 2 to 32
- Input data widths from 4 to 32 bits
- Coefficient widths from 4 to 32 bits
- Signed or unsigned data and coefficients
- Selectable rounding: truncation, rounding away from zero, convergent rounding
- Optional saturation logic for overflow handling
- Full precision arithmetic
- Specification of fractional inputs and outputs
- Support for both serial and parallel filters, with user specified degree of parallelism.
- Configurable pipelining to increase performance
- Optimizations based on filter characteristics (symmetry and halfband).
- Handshake signals to facilitate smooth interfacing
Block Diagram
DAFIR-GEN block diagram
Specifications
Identity
Part Number
DAFIR-GEN
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Filters and Transforms IP cores
What is Distributed Arithmetic FIR (DA-FIR) Filter Generator?
Distributed Arithmetic FIR (DA-FIR) Filter Generator is a Filters Transforms IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.
How should engineers evaluate this Filters Transforms?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Filters Transforms IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.