Vendor: Lattice Semiconductor Corp. Category: DDR

DDR SDRAM Controller - Pipelined

The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller tha…

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Overview

The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard DDR SDRAM. The memory controller provides a generic command interface to the user's application. This interface reduces the effort to integrate the module with the remainder of the application and minimizes the need to deal with the DDR SDRAM command interface. The timing parameters for the memory can be set through the signals that are input to the core as part of the configuration interface. This enables switching between different memory devices and modification of timing parameters to suit the application using the same netlist.

Hardware Demo

A hardware demonstration bitstream for this IP core is available for use with the LatticeEC Advanced Evaluation Board. The bitstream, and a complete description of its operation is available for download by clicking the "Design Files" link in the resource box on this page.

Key features

  • Interfaces to industry standard DDR SDRAM devices and modules
  • High-performance DDR 400/333/266/200/133 operation for LatticeECP3, LatticeECP2/M, LatticeECP2/MS and LatticeSC/M devices; DDR 333/266/200/133 operation for LatticeECP/EC devices; and DDR 266/200/133 operation for LatticeXP devices
  • Programmable burst lengths of 2, 4 or 8 for DDR
  • Programmable CAS latency of 2 or 3 cycles for DDR
  • Intelligent bank management to optimize performance by minimizing ACTIVE commands
  • Supports all JEDEC standard DDR commands
  • Two-stage command pipeline to improve throughput
  • Supports both registered and unbuffered DIMM
  • Command burst function with dynamic burst size control
  • Supports all common memory configurations
    • SDRAM data path widths of 8, 16, 24, 32, 40, 48, 56, 64 and 72 bits
    • Variable address widths for different memory devices
    • Up to eight (DDR) chip selects for multiple SO/DIMM support
    • Programmable memory timing parameters
    • Byte-level writing through data mask signals

Block Diagram

DDRCT-GEN block diagram

Specifications

Identity

Part Number
DDRCT-GEN
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Lattice Semiconductor Corp.

Learn more about DDR IP core

DDR3 memory interface controller IP speeds data processing applications

In order to fully capitalize on the benefits of DDR3 memories, it is important to have an efficient and easy to use DDR3 memory interface controller. A video processing application provides a good example of the key requirements of a DDR3 memory system and the features needed from a DDR3 Interface in similar stream-oriented data processing systems.

Microcontroller Design in FPGAs

The union of Microcontroller Unit (MCU) intellectual property (IP) cores with FPGAs provides a far more flexible hardware platform than traditional MCU ASSPs.

Frequently asked questions about DDR Interface IP

What is DDR SDRAM Controller - Pipelined?

DDR SDRAM Controller - Pipelined is a DDR IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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