Vendor: Lattice Semiconductor Corp. Category: Channel Coding

Dynamic Block Reed-Solomon Decoder

Reed-Solomon codes are used to perform Forward Error Correction (FEC).

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Overview

Reed-Solomon codes are used to perform Forward Error Correction (FEC). FEC introduces controlled redundancy in the data before it is transmitted to allow error correction at the receiver. The redundant data (check symbols) are transmitted with the original data to the receiver. A Reed-Solomon decoder is used in the receiver to correct any transmission errors. This type of error correction is widely used in data communications applications such as Digital Video Broadcasting (DVB) and Optical Carriers (i.e. OC-192).

Lattice’s Dynamic Block Reed-Solomon Decoder IP is compliant with several industry standards including the more recent IEEE 802.16-2004 and can be custom configured to support other non-standard applications as well. The Decoder supports a wide range of symbol widths and allows the user to define the field polynomial, generator polynomial and several other parameters. The newer standards like IEEE 802.16-2004 require the use of Reed-Solomon codes with dynamically varying block sizes. Lattice’s Dynamic Block Reed-Solomon Decoder core provides an ideal solution that meets such needs of today’s forward error correction world. This core allows the block size and number of check symbols to be varied dynamically through input ports. This IP core can be used with Lattice’s Dynamic Block Reed-Solomon Encoder for a complete Reed-Solomon code based forward error correction application.

Reed-Solomon codes are written in the format RS(n, k) where k is the number of information symbols and n is the total number of symbols in a codeword or block. Each symbol in the codeword is wsymb bits wide. The Reed-Solomon Decoder performs detection and correction of encoded data available at the receiver after demodulation. The RS encoded data is then processed to determine whether any errors have occurred during transmission. Once the number of errors is determined, the decoder decides if they are within the range of correction. After determining this, the decoder corrects the errors in the received data. The figure below illustrates the operation of a Reed-Solomon Decoder.

Key features

  • 3 to 12-bit Symbol Width
  • Configurable Field Polynomial
  • Configurable Generator Polynomial: Starting Root and Root Spacing
  • User-defined codewords
    • Maximum of 4095 symbols
    • Maximum of 256 check symbols
    • Shortened codes
  • Support of the following communication standards
    • OC-192
    • DVB
    • CCSDS
    • ATSC
    • IEEE 802.16-2004 WirelessMAN-SCa/OFDM
    • IEEE 802.16-2004 WirelessMAN-SC
  • Fully Synchronous
  • Systematic Decoder
  • Full Handshaking Capability
  • Dynamically Variable Block size
  • Dynamically Variable Check Symbols
  • Error, Erasure, and Puncturing modes
  • Error Measurement information

Block Diagram

RSDEC-DBLK block diagram

Specifications

Identity

Part Number
RSDEC-DBLK
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP

Files

Product Sheet Download

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Provider

Contact Lattice Semiconductor Corp.

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Frequently asked questions about Channel Coding IP cores

What is Dynamic Block Reed-Solomon Decoder?

Dynamic Block Reed-Solomon Decoder is a Channel Coding IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

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