Using FPGAs in Mobile Heterogeneous Computing Architectures
Since "context-aware" systems must be "always on" to track changes in the environment, these capabilities represent a potentially significant drain on system power.
Vendor:
Lattice Semiconductor Corp.
Category:
Channel Coding
Soft Error Detection
Soft errors occur when high-energy charged particles alter the stored charge in a memory cell in an electronic circuit.
Overview
Soft errors occur when high-energy charged particles alter the stored charge in a memory cell in an electronic circuit. The phenomenon first became an issue in DRAM, requiring error detection and correction for large memory systems in high-reliability applications. As device geometries have continued to shrink, the probability of soft errors in SRAM is becoming significant for some systems. Designers are using a variety of approaches to minimize the effects of soft errors on system behavior.
SRAM-based FPGAs store logic configuration data in SRAM cells. As the number and density of SRAM cells in an FPGA increase, the probability that a soft error will alter the programmed logical behavior of the system increases.
The Soft Error Detection is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.
SRAM-based FPGAs store logic configuration data in SRAM cells. As the number and density of SRAM cells in an FPGA increase, the probability that a soft error will alter the programmed logical behavior of the system increases.
The Soft Error Detection is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.
Key features
- 100% detection of single-bit errors
- 100% detection of two-bit errors within 10 adjacent frames
- 100% detection of multiple-bit errors within a 17-bit span
- (1-2-17)*100% detection of random multiple-bit errors
Block Diagram
SED-CORE block diagram
Specifications
Identity
Part Number
SED-CORE
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Channel Coding IP cores
What is Soft Error Detection?
Soft Error Detection is a Channel Coding IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.
How should engineers evaluate this Channel Coding?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.