Altera IP Cores

The Intel® FPGA Video and Vision Processing Suite is a collection of next-generation Intel® FPGA intellectual property (IP) funct…

• Video Processing

Forward-error correction (FEC) channel codes commonly improve the energy efficiency of wireless communication systems.

• Channel Coding

As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the Tone Mapping Operator (TMO) Intel® FPGA IP corrects …

• Video Processing

A numerically controlled oscillator (NCO) is a digital signal generator, which synthesizes a discrete-time, discrete-valued repre…

• Control Logic

The CIC Intel FPGA IP core implements a Cascaded integrator-comb (CIC) filter with data ports that are compatible with the Avalon…

• Filters Transforms

The 5G Polar Intel® FPGA IP implements a forward error correction (FEC) encoder and decoder based on polar codes compliant with t…

• Channel Coding

Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy…

• Channel Coding

The Serial Lite IV Intel® FPGA Intellectual Property (IP) core is suitable for high-bandwidth data communication for chip-to-chip…

• Ethernet

P-Tile is an FPGA companion tile available on Stratix® 10 DX and Agilex™ 7 FPGA F-Series device that natively supports PCIe* conf…

• PCI Express

Stratix® 10 FPGAs incorporate the L/H-Tile chiplets which include a configurable, hardened protocol stack for PCIe that is compli…

• PCI Express

The HDMI Intel FPGA intellectual property (IP) core provides support for the next generation of video display interface technolog…

• HDMI

Ethernet is ubiquitous across many markets and applications.

• Ethernet

Intel now offers a fully VESA-compliant DisplayPort Intel® FPGA IP core v1.4.

• Displayport

The Intel FPGA Video and Image Processing Suite is a collection of Intel FPGA intellectual property (IP) functions that you can u…

• Video Processing

Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels.

• Channel Coding

HBM2E and HBM2 are high-performance memory IPs that offer a combination of high memory bandwidth, low power consumption, low late…

• Controller

Nios® V processors are the next generation of soft processor IPs, designed to bring the power and flexibility of the open-source …

• CPU

IP

• Controller

The QDR II SRAM Controller Intel FPGA IP provides an easy-to-use interface to QDR II SRAM and QDR II+ SRAM modules.

• Controller

The QDR II SRAM Controller Intel® FPGA IP function provides an easy-to-use interface to QDR II SRAM modules.

• Controller