Altera IP Cores

The Multichannel DMA IP for PCI Express provides high efficiency, speed, and configuration flexibility to support various applica…

• PCI Express

The MACsec Intel® FPGA IP core implements the IEEE Media Access Control Security standard as defined in 802.1AE (2018) as fully c…

• MACsec

The Low Latency Ethernet 10G MAC FPGA IP core (soft IP) offers low round-trip latency, and an efficient resource footprint.

• Ethernet

Intel® offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet Intel® FPGA IP core targe…

• Single-Protocol PHY

The JEDEC committee created the JESD204 data converter serial interface standard to standardize and reduce the number of data inp…

• JESD204

The Interlaken Intel® FPGA IP core is Interlaken Protocol Definition v1.2 compliant and allows system developers to achieve high …

• Interlaken

Interlaken Look-Aside is a scalable protocol that allows interoperability between a datapath device and a look-aside coprocessor …

• Interlaken

The enhanced Common Public Radio Interface (eCPRI) Altera® FPGA IP core implements the eCPRI specification version 2.0.

• CPRI

Industry's first FPGA-based hardened CXL IP solution for Type 1, 2, and 3 devices.

• CXL

The Common Public Radio Interface (CPRI) Altera® FPGA IP core implements the CPRI Specification V7.0.

• CPRI

The Backplane Ethernet 10GBASE-KR PHY Intel® FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instant…

• Single-Protocol PHY

The Intel® Agilex™ 7 FPGA F-Tile incorporates a fracturable, configurable, hardened Ethernet protocol stack for supporting rates …

• Ethernet

The Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible …

• Multi-Protocol PHY

The 50G Ethernet Intel® FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Cons…

• Ethernet

The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010.

• Single-Protocol PHY

This IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium.

• Ethernet

The 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding s…

• Single-Protocol PHY

The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device re…

• Single-Protocol PHY

The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection.

• Single-Protocol PHY

As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the Warp Intel® FPGA IP provides a optimized solution fo…

• Video Processing