Altera IP Cores

Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy…

• Channel Coding

The Siemens EDA AXI Verification IP Suite (Intel® FPGA Edition) provides bus functional models (BFMs) to simulate the behavior an…

• Verification IP

DDR4 and DDR5 offer higher bandwidth and improved performance over previous generations, with DDR5 providing further enhancements…

• Controller
• DDR4 + 1

The Serial Lite IV Intel® FPGA Intellectual Property (IP) core is suitable for high-bandwidth data communication for chip-to-chip…

• Ethernet

R-Tile is a FPGA companion tile that supports configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP), and Transaction…

• PCI Express

P-Tile is an FPGA companion tile available on Stratix® 10 DX and Agilex™ 7 FPGA F-Series device that natively supports PCIe* conf…

• PCI Express

Stratix® 10 FPGAs incorporate the L/H-Tile chiplets which include a configurable, hardened protocol stack for PCIe that is compli…

• PCI Express

PCI Express (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 …

• PCI Express

The HDMI Intel FPGA intellectual property (IP) core provides support for the next generation of video display interface technolog…

• HDMI

Ethernet is ubiquitous across many markets and applications.

• Ethernet

Triple Speed Ethernet Triple-Speed Ethernet Intel® FPGA intellectual property (IP) supports the 10 Mbps, 100 Mbps, and 1 Gbps dat…

• Ethernet

Intel now offers a fully VESA-compliant DisplayPort Intel® FPGA IP core v1.4.

• Displayport

The Intel FPGA Video and Image Processing Suite is a collection of Intel FPGA intellectual property (IP) functions that you can u…

• Video Processing

Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels.

• Channel Coding